From nobody Sun May 11 22:09:48 2025 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1516120921700555.0151380438216; Tue, 16 Jan 2018 08:42:01 -0800 (PST) Received: from [127.0.0.1] (helo=ra.coreboot.org) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1ebUKa-0001G9-Tb; Tue, 16 Jan 2018 17:43:24 +0100 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5] helo=mx0a-001b2d01.pphosted.com) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.86_2) (envelope-from ) id 1ebUKC-00017L-Nj for seabios@seabios.org; Tue, 16 Jan 2018 17:43:23 +0100 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w0GGfKlL127799 for ; Tue, 16 Jan 2018 11:41:22 -0500 Received: from e34.co.us.ibm.com (e34.co.us.ibm.com [32.97.110.152]) by mx0b-001b2d01.pphosted.com with ESMTP id 2fhmre16bh-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 16 Jan 2018 11:41:21 -0500 Received: from localhost by e34.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 16 Jan 2018 09:41:12 -0700 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w0GGfBPk12255612; Tue, 16 Jan 2018 09:41:11 -0700 Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8E8AB78043; Tue, 16 Jan 2018 09:41:11 -0700 (MST) Received: from sbct-3.watson.ibm.com (unknown [9.47.158.153]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP id 0D41B78056; Tue, 16 Jan 2018 09:41:10 -0700 (MST) From: Stefan Berger To: seabios@seabios.org Date: Tue, 16 Jan 2018 11:41:03 -0500 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1516120863-13974-1-git-send-email-stefanb@linux.vnet.ibm.com> References: <1516120863-13974-1-git-send-email-stefanb@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18011616-0016-0000-0000-0000081E869A X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008389; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000246; SDB=6.00975916; UDB=6.00494672; IPR=6.00755843; BA=6.00005781; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00019073; XFM=3.00000015; UTC=2018-01-16 16:41:13 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18011616-0017-0000-0000-00003D123666 Message-Id: <1516120863-13974-4-git-send-email-stefanb@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-16_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801160232 X-Spam-Score: -6.5 (------) Subject: [SeaBIOS] [PATCH v2 3/3] tcgbios: extend Physical Presence interface with more functions X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lersek@redhat.com, mst@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Implement more functions of the TPM Physical Presence interface. Some of the added functions will automatically reboot the machine. Thus we need to save the next step after the reboot in an additional variable. Signed-off-by: Stefan Berger --- src/std/tcg.h | 7 ++++++ src/tcgbios.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-= ---- 2 files changed, 71 insertions(+), 5 deletions(-) diff --git a/src/std/tcg.h b/src/std/tcg.h index 22353a9..aeee689 100644 --- a/src/std/tcg.h +++ b/src/std/tcg.h @@ -548,8 +548,15 @@ struct pcctes_romex #define TPM_PPI_OP_ACTIVATE 3 #define TPM_PPI_OP_DEACTIVATE 4 #define TPM_PPI_OP_CLEAR 5 +#define TPM_PPI_OP_ENABLE_ACTIVATE 6 +#define TPM_PPI_OP_DEACTIVATE_DISABLE 7 #define TPM_PPI_OP_SET_OWNERINSTALL_TRUE 8 #define TPM_PPI_OP_SET_OWNERINSTALL_FALSE 9 +#define TPM_PPI_OP_ENABLE_ACTIVATE_SET_OWNERINSTALL_TRUE 10 +#define TPM_PPI_OP_SET_OWNERINSTALL_FALSE_DEACTIVATE_DISABLE 11 +#define TPM_PPI_OP_CLEAR_ENABLE_ACTIVATE 14 +#define TPM_PPI_OP_ENABLE_ACTIVATE_CLEAR 21 +#define TPM_PPI_OP_ENABLE_ACTIVATE_CLEAR_ENABLE_ACTIVATE 22 =20 struct tpm_ppi { u8 ppin; /* 0: 1 =3D initialized */ diff --git a/src/tcgbios.c b/src/tcgbios.c index c8e6ca2..e074d42 100644 --- a/src/tcgbios.c +++ b/src/tcgbios.c @@ -1655,7 +1655,8 @@ tpm12_set_owner_install(int allow, int verbose, u32 *= returnCode) } =20 static int -tpm12_process_cfg(tpm_ppi_code msgCode, int verbose, u32 *returnCode) +tpm12_process_cfg(tpm_ppi_code msgCode, int verbose, u32 *returnCode, + u8 *nextStep) { int ret =3D 0; =20 @@ -1683,6 +1684,18 @@ tpm12_process_cfg(tpm_ppi_code msgCode, int verbose,= u32 *returnCode) ret =3D tpm12_force_clear(1, 0, verbose, returnCode); break; =20 + case TPM_PPI_OP_ENABLE_ACTIVATE: + ret =3D tpm12_enable_tpm(1, verbose, returnCode); + if (!ret) + ret =3D tpm12_activate_tpm(1, 1, verbose, returnCode); + break; + + case TPM_PPI_OP_DEACTIVATE_DISABLE: + ret =3D tpm12_activate_tpm(0, 1, verbose, returnCode); + if (!ret) + ret =3D tpm12_enable_tpm(0, verbose, returnCode); + break; + case TPM_PPI_OP_SET_OWNERINSTALL_TRUE: ret =3D tpm12_set_owner_install(1, verbose, returnCode); break; @@ -1691,6 +1704,43 @@ tpm12_process_cfg(tpm_ppi_code msgCode, int verbose,= u32 *returnCode) ret =3D tpm12_set_owner_install(0, verbose, returnCode); break; =20 + case TPM_PPI_OP_ENABLE_ACTIVATE_SET_OWNERINSTALL_TRUE: + *nextStep =3D TPM_PPI_OP_SET_OWNERINSTALL_TRUE; + ret =3D tpm12_enable_activate(1, verbose, returnCode); + if (!ret) + ret =3D tpm12_set_owner_install(1, verbose, returnCode); + break; + + case TPM_PPI_OP_SET_OWNERINSTALL_FALSE_DEACTIVATE_DISABLE: + ret =3D tpm12_set_owner_install(0, verbose, returnCode); + if (!ret) + ret =3D tpm12_activate_tpm(0, 0, verbose, returnCode); + if (!ret) + ret =3D tpm12_enable_tpm(0, verbose, returnCode); + break; + + case TPM_PPI_OP_CLEAR_ENABLE_ACTIVATE: + ret =3D tpm12_force_clear(0, 1, verbose, returnCode); + break; + + case TPM_PPI_OP_ENABLE_ACTIVATE_CLEAR: + *nextStep =3D TPM_PPI_OP_CLEAR; + ret =3D tpm12_enable_activate(1, verbose, returnCode); + /* no reboot happened */ + if (!ret) + ret =3D tpm12_force_clear(0, 0, verbose, returnCode); + break; + + case TPM_PPI_OP_ENABLE_ACTIVATE_CLEAR_ENABLE_ACTIVATE: + *nextStep =3D TPM_PPI_OP_CLEAR_ENABLE_ACTIVATE; + ret =3D tpm12_enable_activate(1, verbose, returnCode); + /* no reboot happened */ + if (!ret) { + *nextStep =3D TPM_PPI_OP_NOOP; + ret =3D tpm12_force_clear(0, 1, verbose, returnCode); + } + break; + default: break; } @@ -1783,11 +1833,12 @@ tpm20_process_cfg(tpm_ppi_code msgCode, int verbose= , u32 *returnCode) } =20 static int -tpm_process_cfg(tpm_ppi_code msgCode, int verbose, u32 *returnCode) +tpm_process_cfg(tpm_ppi_code msgCode, int verbose, u32 *returnCode, + u8 *nextStep) { switch (TPM_version) { case TPM_VERSION_1_2: - return tpm12_process_cfg(msgCode, verbose, returnCode); + return tpm12_process_cfg(msgCode, verbose, returnCode, nextStep); case TPM_VERSION_2: return tpm20_process_cfg(msgCode, verbose, returnCode); } @@ -1959,7 +2010,8 @@ tpm12_menu(void) break; =20 if (next_scancodes[i] =3D=3D scancode) { - tpm12_process_cfg(msgCode, 1, NULL); + u8 ignore; + tpm12_process_cfg(msgCode, 1, NULL, &ignore); waitkey =3D 0; break; } @@ -2049,8 +2101,15 @@ static const u8 tpm12_ppi_funcs[] =3D { [TPM_PPI_OP_ACTIVATE] =3D FLAGS, [TPM_PPI_OP_DEACTIVATE] =3D FLAGS, [TPM_PPI_OP_CLEAR] =3D FLAGS, + [TPM_PPI_OP_ENABLE_ACTIVATE] =3D FLAGS, + [TPM_PPI_OP_DEACTIVATE_DISABLE] =3D FLAGS, [TPM_PPI_OP_SET_OWNERINSTALL_TRUE] =3D FLAGS, [TPM_PPI_OP_SET_OWNERINSTALL_FALSE] =3D FLAGS, + [TPM_PPI_OP_ENABLE_ACTIVATE_SET_OWNERINSTALL_TRUE] =3D FLAGS, + [TPM_PPI_OP_SET_OWNERINSTALL_FALSE_DEACTIVATE_DISABLE] =3D FLAGS, + [TPM_PPI_OP_CLEAR_ENABLE_ACTIVATE] =3D FLAGS, + [TPM_PPI_OP_ENABLE_ACTIVATE_CLEAR] =3D FLAGS, + [TPM_PPI_OP_ENABLE_ACTIVATE_CLEAR_ENABLE_ACTIVATE] =3D FLAGS, }; =20 static const u8 tpm2_ppi_funcs[] =3D { @@ -2116,7 +2175,7 @@ tpm_ppi_process(void) tp->pprq =3D 0; =20 printf("Processing TPM PPI opcode %d\n", op); - tpm_process_cfg(op, 0, &tp->pprp); + tpm_process_cfg(op, 0, &tp->pprp, &nextStep); } } } --=20 2.5.5 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios