From nobody Sat May 10 08:06:33 2025 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1533177609528199.98992943479527; Wed, 1 Aug 2018 19:40:09 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coreboot.org) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1fl3YZ-0001NN-06; Thu, 02 Aug 2018 04:41:39 +0200 Received: from mail-wr1-f65.google.com ([209.85.221.65]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1fl3YL-0001Mq-FV for seabios@seabios.org; Thu, 02 Aug 2018 04:41:36 +0200 Received: by mail-wr1-f65.google.com with SMTP id j5-v6so522339wrr.8 for ; Wed, 01 Aug 2018 19:39:31 -0700 (PDT) Received: from bloodymary.ipads-lab.se.sjtu.edu.cn ([46.243.138.172]) by smtp.gmail.com with ESMTPSA id a84-v6sm380965wmh.27.2018.08.01.19.39.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 01 Aug 2018 19:39:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WPxHEHnOpip4IVkRGvwHs+/lwomtZWyAp9yzvgaxhaE=; b=hD46CoIhvUaXtMA9/j+Osl9nxH8rzwa0IZCzP0pnSd6otgUMnuSHcI34HSPCzkAi9Y M4VdJ9HXZoPEOm+SZaY0raaNmCegq8z9s5ldj8OkhSGppXDX8/CWS0NPPtVjIPienuTq i3fW91JU53xXK1Vk3H7d4Bf1Fflj5hISqJxmNEXVBFVF1rjE7xpbZyGd1Z4PnUpEU3Wy WxcXGHLXI1GUhLf5hbUgtXz8LRt/KJdL7SDBek41PeRWEOhtQTgBB+5Nf9RmM537zI4F 8iHE1/qvH0bIjmCO2+F8QwyZ++P2n67mUeSk/jL3TVyg8H7H6dKexxqI94diMAwZi0iw 3p7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WPxHEHnOpip4IVkRGvwHs+/lwomtZWyAp9yzvgaxhaE=; b=q+TBt9QeuDF6eAu1vAUB3DIsZqkE/adPi9ui/VMKFH04BlheyN9scSj7L2WSirD5j9 K8BVREAGNORDmIHOZTfxEhEJyA+pCjRJbq+IGlCXb3s1NNOgJ2VECpDXCv6dzcM+nNyC uizjZA75S0hZB5hcpOd0ueRKzanBWi263dSPp3dcGjAy+Gt/UCRzfkX43Xf3W91WHt4o SlSNOrwkUZp9UvchE2xl7/nNkVdZzB1jbPqTT4qvJSqZSV+bT7fVeHutinhEyAOVSldn ZUhSUOgtEDBmhPmn/qwWGjppsUPIbS/7L202O0en7BdLEpkr0bBtknloPJD/HeGSf9q4 LBNg== X-Gm-Message-State: AOUpUlHdZTsJWzbvIck5139k6tR+FEqM+F4xsDArMX7JDiSxteU68ewp wi/2bEBMZzlhCrq0WLYJK39sSEwU3Mc= X-Google-Smtp-Source: AAOMgpcfU6KTGQfF3TKImnP6Pk8pZyL/CYg9CpRMP/fgAFDtHDU4tguZnpb3k3rggLkeLvin3CzwBA== X-Received: by 2002:adf:9aa3:: with SMTP id a32-v6mr523220wrc.75.1533177570004; Wed, 01 Aug 2018 19:39:30 -0700 (PDT) From: Zihan Yang To: seabios@seabios.org Date: Thu, 2 Aug 2018 10:39:14 +0800 Message-Id: <1533177555-19114-2-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533177555-19114-1-git-send-email-whois.zihan.yang@gmail.com> References: <1533177555-19114-1-git-send-email-whois.zihan.yang@gmail.com> X-Spam-Score: -3.5 (---) Subject: [SeaBIOS] [RFC 1/2] fw/pciinit: Recognize pxb-pcie-dev device X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" QEMU q35 uses pxb-pcie-dev to enable multiple host bridges, this patch recognizes such devices in seabios and add corresponding e820 entry. MCFG base and size are already setup in QEMU, we just need to read it Signed-off-by: Zihan Yang --- src/fw/paravirt.c | 1 - src/fw/pciinit.c | 17 +++++++++++++++++ src/hw/pci_ids.h | 1 + 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index 0770c47..6b14542 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -197,7 +197,6 @@ qemu_platform_setup(void) if (!loader_err) warn_internalerror(); } - acpi_setup(); } =20 diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 3a2f747..6e6a434 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -507,11 +507,28 @@ static void mch_mem_addr_setup(struct pci_device *dev= , void *arg) pci_io_low_end =3D acpi_pm_base; } =20 +static void pxb_mem_addr_setup(struct pci_device *dev, void *arg) +{ + union u64_u32_u mcfg_base; + mcfg_base.lo =3D pci_config_readl(dev->bdf, Q35_HOST_BRIDGE_PCIEXBAR); + mcfg_base.hi =3D pci_config_readl(dev->bdf, Q35_HOST_BRIDGE_PCIEXBAR += 4); + + // Fix me! Use another meaningful macro + u32 mcfg_size =3D pci_config_readl(dev->bdf, Q35_HOST_BRIDGE_PCIEXBAR = + 8); + + /* Skip config write here as the qemu-level objects are already setup,= we + * read mcfg_base and mcfg_size from it just now. Instead, we directly= add + * this item to e820 */ + e820_add(mcfg_base.val, mcfg_size, E820_RESERVED); +} + static const struct pci_device_id pci_platform_tbl[] =3D { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, i440fx_mem_addr_setup), PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH, mch_mem_addr_setup), + PCI_DEVICE(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_PXB_HOST, + pxb_mem_addr_setup), PCI_DEVICE_END }; =20 diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 38fa2ca..35096ea 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2265,6 +2265,7 @@ =20 #define PCI_VENDOR_ID_REDHAT 0x1b36 #define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C +#define PCI_DEVICE_ID_REDHAT_PXB_HOST 0x000B =20 #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios