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[71.65.111.223]) by smtp.googlemail.com with ESMTPSA id l1sm16018572qkj.101.2020.12.08.13.26.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Dec 2020 13:26:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TekqjgSsdWTRJUqcm3lBG19qprznIlJibNa9BIZ8520=; b=lwl8B0bvflCaiP9+PZSNj3AqNQK7cGYKAQg2JWnnvbzy6NXBhn45+8CtanCzmgz6q8 Rk8fd4LySvXbvYKm0oHWkpW/kt3GOMe5O1lpZvxYMKgHZmUXzZSJL2sr/73PQcxgn6U3 NZr7/d/oKDT2SOulNog3GdaH4unxs/tMQTEJUqROr/fK/CzxY+plvWlKXqtM/PgGAEfj EieJCci//nxViPUIcBYqoTw2LKP6tcCBc0/sRKKtSE/W8lYY+Kje30MnWfWwsQWsslNO EWS/icQaVCbExyj2/J725suZNOvTJjDGXZgYBsnDjplJw8KylPAwU1VSqfb/4LkVzScF fHSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TekqjgSsdWTRJUqcm3lBG19qprznIlJibNa9BIZ8520=; b=GldIop9xfIjqTZJg5KcO2HCzz2sbf0shLkOXI/OyzbpKguSbu2S7NXAVw5GE3V8iI7 z0eyDc7lZzQcDX8T4e4AFYQLNWnsF3/PCk0jjY8E1hHqwAEI0rI6EY20hPa8IQQTU2aH 3L+UDteBVJjwk9zu1d4u6DA1KzhFxDDPKEr5vO99p1dPCq/nd427osDxe+wi+4mIB4xN 9Z7QLb2/+JNSBwTPfWBMt0wxzpWz3UHBh1L4+NluOKKpkzVqptKLF/IWi+zPig5n/Q74 uVx8SQeHan+CWqJ6sgvxrskQI04zApdT74b/u8GAsdb8k8wYYENZB0swF+EydALLOb9k t/uA== X-Gm-Message-State: AOAM531zJAjBVltRVwsXbRe+m9hKfM9BTKKgyGYIWQ+aNhObC7HAYWmG fOi3TB9mda5F97lurtTHO4k= X-Google-Smtp-Source: ABdhPJzGjv4tMTGgPbFeKpWWjYQoYNBsAo5cAtcyK8NsnwzCDbyjGdGmRJgjvOj/PyFNv9Qr4f5vQA== X-Received: by 2002:ac8:6f04:: with SMTP id g4mr26375008qtv.122.1607462781299; Tue, 08 Dec 2020 13:26:21 -0800 (PST) From: Connor McAdams Cc: conmanx360@gmail.com, Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] ALSA: hda/ca0132 - Reset codec upon initialization. Date: Tue, 8 Dec 2020 16:25:41 -0500 Message-Id: <20201208212546.428392-2-conmanx360@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208212546.428392-1-conmanx360@gmail.com> References: <20201208212546.428392-1-conmanx360@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Reset the codec upon initialization to clear out anything that may have been setup on a previous boot into Windows, or in case of an improper shutdown. Signed-off-by: Connor McAdams --- sound/pci/hda/patch_ca0132.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 4fbec4258f58..05945f021e74 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -8642,6 +8642,22 @@ static void ca0132_init_chip(struct hda_codec *codec) =20 mutex_init(&spec->chipio_mutex); =20 + /* + * The Windows driver always does this upon startup, which seems to + * clear out any previous configuration. This should help issues where + * a boot into Windows prior to a boot into Linux breaks things. Also, + * Windows always sends the reset twice. + */ + if (ca0132_use_alt_functions(spec)) { + chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); + chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2); + + snd_hda_codec_write(codec, codec->core.afg, 0, + AC_VERB_SET_CODEC_RESET, 0); + snd_hda_codec_write(codec, codec->core.afg, 0, + AC_VERB_SET_CODEC_RESET, 0); + } + spec->cur_out_type =3D SPEAKER_OUT; if (!ca0132_use_alt_functions(spec)) spec->cur_mic_type =3D DIGITAL_MIC; @@ -9262,11 +9278,6 @@ static void ae5_register_set(struct hda_codec *codec) =20 if (ca0132_quirk(spec) =3D=3D QUIRK_AE5) ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); - - chipio_write(codec, 0x18b0a4, 0x000000c2); - - snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); - snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); } =20 /* --=20 2.25.1 From nobody Sat May 10 02:37:35 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607462873; cv=none; d=zohomail.com; s=zohoarc; b=a1YAfsfYeqigqRKp1XamHFEQvXx6JeEhulo0TBqvYa/dllD2J2kBuExVj/OJjfmrjvhMFdC9gNc9kR4/+wRlG0emGHxnNFaRsClGHIJuqAavT/AyIVFp4MlISPhR1KCxjQuB8NKVdpc6kHRHFjrx6PCMgkA4qlH7ZdC98k7XuSk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607462873; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=SQZSEHpGW/GYcr7MQXvzQqIae6S9onjjJE5GGoch4P4=; b=jEe5W/9vEeMrYikoICbpISnGbMy8a/bGbQdE0DBO8jmD4Gompnd0Miksc02L8u32puSQOwF6cEbk+MkwF7KBK5RKHXWCt+LugY5dpBM2OPjiTa8luZmBxWZ7C4J2pAHyX48iAZ57I7eTWRVblhk5rAoDcy70LEAK2yalO5mwPDc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1607462873521141.3742247740787; Tue, 8 Dec 2020 13:27:53 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729769AbgLHV1H (ORCPT ); Tue, 8 Dec 2020 16:27:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726104AbgLHV1E (ORCPT ); Tue, 8 Dec 2020 16:27:04 -0500 Received: from mail-qt1-x841.google.com (mail-qt1-x841.google.com [IPv6:2607:f8b0:4864:20::841]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C99AC061794 for ; Tue, 8 Dec 2020 13:26:24 -0800 (PST) Received: by mail-qt1-x841.google.com with SMTP id y15so5493720qtv.5 for ; Tue, 08 Dec 2020 13:26:24 -0800 (PST) Received: from localhost.localdomain (cpe-71-65-111-223.cinci.res.rr.com. [71.65.111.223]) by smtp.googlemail.com with ESMTPSA id l1sm16018572qkj.101.2020.12.08.13.26.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Dec 2020 13:26:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SQZSEHpGW/GYcr7MQXvzQqIae6S9onjjJE5GGoch4P4=; b=U3Or7+5B68M/cY3xNm+3fseQgwQgwyGg3HMnYQeYeNM5fpBiOrfynkEzBL7nShcJJg aGGNDMbXKk6RBeE82WrasGMqmvUgiloGxAiTPD3SqjxCn/ab4rEOUHA5fvYYIFO3k+8B F8LkeL3NubvKUMIQneOUYrLWQAXCodpu37X7wdEyblKByo79mUm1ytisARsBuzBkbofh aS5Bis9hW4YyB2/SFHFUCWzGepIlWPmppIe5cFdm+5NHmYau2VLgrnsncVXvu9BGGntY DkW6Y9tPeOm7tVZjF+fhB9Xage7Nf0kR+Ha8GTtfdDQIfmBb5iHaOvtITHYiT2oGZ+cS 7MBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SQZSEHpGW/GYcr7MQXvzQqIae6S9onjjJE5GGoch4P4=; b=UiySFFJG6Y7aSQa2FmOW5fvodD2libI47j//eU6zg7lixvEhBsFQ0gmDyx0+tJo9y4 QrzNCD3kF4ET2ZoczfDfYJE/sGu/PBHOD640g6ockqMVc5TlpTPw2j6gMr6ZVWrU67VH dlmuNjyhkaPWQPof1Sp8ZD22Ols6wBFOqDbzPXnGn+kJMZr3gxTc1PN23maGOKr08gpK B656zJ2x87vh7nNNWXlBWNwgkDHciVEymNb1hBHYkxLPwKhPiSJpgipV+zUWYpMAgCkT C6i1ELDZj36eFISnmfebnqD4eGCmkqtNBnMFGFHSrgAjwNt7jv/6NqJdyI5OqqVC0zGV qWXQ== X-Gm-Message-State: AOAM533gr+Q3NLiU6i8d4Mt/VZkklupo2Ock24mNsEYRxoUoTZsQnBnt QAp7exnbv9PzYVpDtSEypv0= X-Google-Smtp-Source: ABdhPJzrCScETkAQkxrW4WASil2rnrve5p3O1xp2HzI4IVhwAzZMvf7ci54Eov4ZguUtf7aj2sTGSQ== X-Received: by 2002:aed:3b93:: with SMTP id r19mr27725103qte.222.1607462783517; Tue, 08 Dec 2020 13:26:23 -0800 (PST) From: Connor McAdams Cc: conmanx360@gmail.com, Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] ALSA: hda/ca0132 - Add stream port remapping function. Date: Tue, 8 Dec 2020 16:25:42 -0500 Message-Id: <20201208212546.428392-3-conmanx360@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208212546.428392-1-conmanx360@gmail.com> References: <20201208212546.428392-1-conmanx360@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add function for remapping a ChipIO stream's ports. Also include some documentation as to how this works. Signed-off-by: Connor McAdams --- sound/pci/hda/patch_ca0132.c | 208 ++++++++++++++++++++++++++--------- 1 file changed, 156 insertions(+), 52 deletions(-) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 05945f021e74..650a7e2bd311 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -788,6 +788,40 @@ static const struct ae5_filter_set ae5_filter_presets[= ] =3D { } }; =20 +/* + * Data structures for storing audio router remapping data. These are used= to + * remap a currently active streams ports. + */ +struct chipio_stream_remap_data { + unsigned int stream_id; + unsigned int count; + + unsigned int offset[16]; + unsigned int value[16]; +}; + +static const struct chipio_stream_remap_data stream_remap_data[] =3D { + { .stream_id =3D 0x14, + .count =3D 0x04, + .offset =3D { 0x00, 0x04, 0x08, 0x0c }, + .value =3D { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 }, + }, + { .stream_id =3D 0x0c, + .count =3D 0x0c, + .offset =3D { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, + 0x20, 0x24, 0x28, 0x2c }, + .value =3D { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, + 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7, + 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb }, + }, + { .stream_id =3D 0x0c, + .count =3D 0x08, + .offset =3D { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c }, + .value =3D { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5, + 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb }, + } +}; + enum hda_cmd_vendor_io { /* for DspIO node */ VENDOR_DSPIO_SCP_WRITE_DATA_LOW =3D 0x000, @@ -7423,6 +7457,104 @@ static void ca0132_refresh_widget_caps(struct hda_c= odec *codec) } } =20 +/* + * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio + * router', where each entry represents a 48khz audio channel, with a form= at + * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number + * value. The 2-bit number value is seemingly 0 if inactive, 1 if active, + * and 3 if it's using Sample Rate Converter ports. + * An example is: + * 0x0001f8c0 + * In this case, f8 is the destination, and c0 is the source. The number v= alue + * is 1. + * This region of memory is normally managed internally by the 8051, where + * the region of exram memory from 0x1477-0x1575 has each byte represent an + * entry within the 0x190000 range, and when a range of entries is in use,= the + * ending value is overwritten with 0xff. + * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO + * streamID's, where each entry is a starting 0x190000 port offset. + * 0x159d in exram is the same as 0x1578, except it contains the ending po= rt + * offset for the corresponding streamID. + * + * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by + * the 8051, then manually overwritten to remap the ports to work with the + * new DACs. + * + * Currently known portID's: + * 0x00-0x1f: HDA audio stream input/output ports. + * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to + * have the lower-nibble set to 0x1, 0x2, and 0x9. + * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned. + * 0xe0-0xff: DAC/ADC audio input/output ports. + * + * Currently known streamID's: + * 0x03: Mic1 ADC to DSP. + * 0x04: Mic2 ADC to DSP. + * 0x05: HDA node 0x02 audio stream to DSP. + * 0x0f: DSP Mic exit to HDA node 0x07. + * 0x0c: DSP processed audio to DACs. + * 0x14: DAC0, front L/R. + * + * It is possible to route the HDA audio streams directly to the DAC and + * bypass the DSP entirely, with the only downside being that since the DSP + * does volume control, the only volume control you'll get is through PCM = on + * the PC side, in the same way volume is handled for optical out. This ma= y be + * useful for debugging. + */ +static void chipio_remap_stream(struct hda_codec *codec, + const struct chipio_stream_remap_data *remap_data) +{ + unsigned int i, stream_offset, tmp; + + /* Get the starting port for the stream to be remapped. */ + tmp =3D 0x1578 + remap_data->stream_id; + for (i =3D 0; i < 2; i++) { + snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_ADDRESS_LOW + i, + ((tmp >> (i * 8)) & 0xff)); + } + + stream_offset =3D snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_DATA_READ, 0); + + /* + * Check if the stream's port value is 0xff, because the 8051 may not + * have gotten around to setting up the stream yet. Wait until it's + * setup to remap it's ports. + */ + if (stream_offset =3D=3D 0xff) { + for (i =3D 0; i < 5; i++) { + msleep(25); + + stream_offset =3D snd_hda_codec_read(codec, + WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_DATA_READ, 0); + + if (stream_offset !=3D 0xff) + break; + } + } + + if (stream_offset =3D=3D 0xff) { + codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap faile= d!\n", + __func__, remap_data->stream_id); + return; + } + + /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */ + stream_offset *=3D 0x04; + stream_offset +=3D 0x190000; + + for (i =3D 0; i < remap_data->count; i++) { + chipio_write_no_mutex(codec, + stream_offset + remap_data->offset[i], + remap_data->value[i]); + } + + /* Update stream map configuration. */ + chipio_write_no_mutex(codec, 0x19042c, 0x00000001); +} + /* * Default speaker tuning values setup for alternative codecs. */ @@ -7570,46 +7702,35 @@ static void sbz_connect_streams(struct hda_codec *c= odec) */ static void sbz_chipio_startup_data(struct hda_codec *codec) { + const struct chipio_stream_remap_data *dsp_out_remap_data; struct ca0132_spec *spec =3D codec->spec; =20 mutex_lock(&spec->chipio_mutex); codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); =20 - /* These control audio output */ - chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); - chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); - chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); - chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); - /* Signal to update I think */ - chipio_write_no_mutex(codec, 0x19042c, 0x00000001); + /* Remap DAC0's output ports. */ + chipio_remap_stream(codec, &stream_remap_data[0]); =20 - chipio_set_stream_channels(codec, 0x0C, 6); - chipio_set_stream_control(codec, 0x0C, 1); - /* No clue what these control */ - if (ca0132_quirk(spec) =3D=3D QUIRK_SBZ) { - chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); - chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); - chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); - chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); - chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); - chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); - chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); - chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); - chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); - chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); - chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); - chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); - } else if (ca0132_quirk(spec) =3D=3D QUIRK_ZXR) { - chipio_write_no_mutex(codec, 0x190038, 0x000140c2); - chipio_write_no_mutex(codec, 0x19003c, 0x000141c3); - chipio_write_no_mutex(codec, 0x190040, 0x000150c4); - chipio_write_no_mutex(codec, 0x190044, 0x000151c5); - chipio_write_no_mutex(codec, 0x190050, 0x000142c8); - chipio_write_no_mutex(codec, 0x190054, 0x000143c9); - chipio_write_no_mutex(codec, 0x190058, 0x000152ca); - chipio_write_no_mutex(codec, 0x19005c, 0x000153cb); + /* Remap DSP audio output stream ports. */ + switch (ca0132_quirk(spec)) { + case QUIRK_SBZ: + dsp_out_remap_data =3D &stream_remap_data[1]; + break; + + case QUIRK_ZXR: + dsp_out_remap_data =3D &stream_remap_data[2]; + break; + + default: + dsp_out_remap_data =3D NULL; + break; } - chipio_write_no_mutex(codec, 0x19042c, 0x00000001); + + chipio_set_stream_channels(codec, 0x0c, 6); + chipio_set_stream_control(codec, 0x0c, 1); + + if (dsp_out_remap_data) + chipio_remap_stream(codec, dsp_out_remap_data); =20 codec_dbg(codec, "Startup Data exited, mutex released.\n"); mutex_unlock(&spec->chipio_mutex); @@ -7842,34 +7963,17 @@ static void ae5_post_dsp_startup_data(struct hda_co= dec *codec) mutex_unlock(&spec->chipio_mutex); } =20 -static const unsigned int ae7_port_set_data[] =3D { - 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 0x0001e2c4, 0x0001e3c5, - 0x0001e8c6, 0x0001e9c7, 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb -}; - static void ae7_post_dsp_setup_ports(struct hda_codec *codec) { struct ca0132_spec *spec =3D codec->spec; - unsigned int i, count, addr; =20 mutex_lock(&spec->chipio_mutex); =20 chipio_set_stream_channels(codec, 0x0c, 6); chipio_set_stream_control(codec, 0x0c, 1); =20 - count =3D ARRAY_SIZE(ae7_port_set_data); - addr =3D 0x190030; - for (i =3D 0; i < count; i++) { - chipio_write_no_mutex(codec, addr, ae7_port_set_data[i]); - - /* Addresses are incremented by 4-bytes. */ - addr +=3D 0x04; - } - - /* - * Port setting always ends with a write of 0x1 to address 0x19042c. - */ - chipio_write_no_mutex(codec, 0x19042c, 0x00000001); + /* Seems to share the same port remapping as the SBZ. */ + chipio_remap_stream(codec, &stream_remap_data[1]); =20 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); --=20 2.25.1 From nobody Sat May 10 02:37:35 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; 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[71.65.111.223]) by smtp.googlemail.com with ESMTPSA id l1sm16018572qkj.101.2020.12.08.13.26.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Dec 2020 13:26:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XsyJ3gRTYQTAHCmnlDsIOFfZYOcu+GEmry0fZOE/64g=; b=ouekelFvEGX4aWZ0CakOks1nK7SgGIo3nLeWVGG6Rqckiqqf2JL+udHXM27b01EGTa R/IixshboMWM1uHCkG6iT9LGJODk78beR8NsMpN9Z8ZSphrI+no3e6iOzI6OjXqbP+Py QphZNjPmiMEsmq8CWKGbNWG7qeTFdhHE67Ng1UU4PW+TiMpV5UEPACAaRU7Ny10RfRvL uE27JDGgcJYTvJHJu/Ung9Smm7CbGYwZsASncTonRgiQY7+ObOs8dH7EM+JwoZ1VtLU8 +nlnLoBxjZzBHK9ymN0yd6wZshTrbsEvG+dizGwAUecpxTGv9NZoS3e5qW5IHecAuIfw Xb1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XsyJ3gRTYQTAHCmnlDsIOFfZYOcu+GEmry0fZOE/64g=; b=sWCLHfXgx8hLkSHBnQv6KYiWlVuYzhoFqlnesSX7uk7P2aGLUY6RYimzp6iWLUZ7zG zUpKakPLBA0rSzm44ELbe0/PAMiyqOHXx0ISOAW9nzagaoH+GvRRgejTg3DLk71i0dRP Y13PTsfupxBwRd0PGZuExqORNbdkaRVPD74sb7kUvsh9sCYNmBPEomADV3KPOSQZwRf3 /z8n01rWPDWZKI4umA3kbFBRCm8eZhU8J0mX8z8b2jLxyCu3F2styObfYiai7JaYQxF1 sk5dzD/q5JNvYrVDiLjMuXjdDSVOGTl1B0vqbJOZChBx4/1r/J7mswa/7/0iQSbJTYyF Tq7w== X-Gm-Message-State: AOAM5303s1Dzof/rNreC200iz+yt4LPYnPgi1kbiCQzH5+Br8xervSHd TsB5fLtgcvyKJbZhEgukxcg= X-Google-Smtp-Source: ABdhPJwRqfeo69ee1GtzvXdcEFMUHjl9hP2aNtT+aDgUwXl5+wpPulO6P2XaFWGE5coAuEkdM/ftDA== X-Received: by 2002:a37:a315:: with SMTP id m21mr14315303qke.279.1607462785552; Tue, 08 Dec 2020 13:26:25 -0800 (PST) From: Connor McAdams Cc: conmanx360@gmail.com, Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] ALSA: hda/ca0132 - Add 8051 exram helper functions. Date: Tue, 8 Dec 2020 16:25:43 -0500 Message-Id: <20201208212546.428392-4-conmanx360@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208212546.428392-1-conmanx360@gmail.com> References: <20201208212546.428392-1-conmanx360@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add functions for both reading and writing to the 8051's exram. Also, add a little bit of documentation on how the addresses are segmented. Signed-off-by: Connor McAdams --- sound/pci/hda/patch_ca0132.c | 138 ++++++++++++++++++++--------------- 1 file changed, 80 insertions(+), 58 deletions(-) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 650a7e2bd311..cb725586d38b 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -1901,6 +1901,71 @@ static void chipio_8051_write_direct(struct hda_code= c *codec, snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); } =20 +/* + * Writes to the 8051's exram, which has 16-bits of address space. + * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff. + * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by + * setting the pmem bank selection SFR. + * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xff= ff + * being writable. + */ +static void chipio_8051_write_exram(struct hda_codec *codec, + unsigned int addr, unsigned int data, bool use_mutex) +{ + struct ca0132_spec *spec =3D codec->spec; + unsigned int tmp; + + if (use_mutex) + mutex_lock(&spec->chipio_mutex); + + /* Lower 8-bits. */ + tmp =3D addr & 0xff; + snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); + + /* Upper 8-bits. */ + tmp =3D (addr >> 8) & 0xff; + snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); + + /* 8-bits of data. */ + tmp =3D data & 0xff; + snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_DATA_WRITE, tmp); + + if (use_mutex) + mutex_unlock(&spec->chipio_mutex); +} + +/* Readback data from the 8051's exram. */ +static void chipio_8051_read_exram(struct hda_codec *codec, + unsigned int addr, unsigned int *data, bool use_mutex) +{ + struct ca0132_spec *spec =3D codec->spec; + unsigned int tmp; + + if (use_mutex) + mutex_lock(&spec->chipio_mutex); + + /* Lower 8-bits. */ + tmp =3D addr & 0xff; + snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); + + /* Upper 8-bits. */ + tmp =3D (addr >> 8) & 0xff; + snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); + + /* 8-bits of data. */ + *data =3D snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_DATA_READ, + 0); + + if (use_mutex) + mutex_unlock(&spec->chipio_mutex); +} + /* * Enable clocks. */ @@ -7422,18 +7487,10 @@ static void ca0132_init_analog_mic2(struct hda_code= c *codec) struct ca0132_spec *spec =3D codec->spec; =20 mutex_lock(&spec->chipio_mutex); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); + + chipio_8051_write_exram(codec, 0x1920, 0x00, false); + chipio_8051_write_exram(codec, 0x192d, 0x00, false); + mutex_unlock(&spec->chipio_mutex); } =20 @@ -7504,18 +7561,11 @@ static void ca0132_refresh_widget_caps(struct hda_c= odec *codec) static void chipio_remap_stream(struct hda_codec *codec, const struct chipio_stream_remap_data *remap_data) { - unsigned int i, stream_offset, tmp; + unsigned int i, stream_offset; =20 /* Get the starting port for the stream to be remapped. */ - tmp =3D 0x1578 + remap_data->stream_id; - for (i =3D 0; i < 2; i++) { - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW + i, - ((tmp >> (i * 8)) & 0xff)); - } - - stream_offset =3D snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_READ, 0); + chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, + &stream_offset, false); =20 /* * Check if the stream's port value is 0xff, because the 8051 may not @@ -7526,9 +7576,8 @@ static void chipio_remap_stream(struct hda_codec *cod= ec, for (i =3D 0; i < 5; i++) { msleep(25); =20 - stream_offset =3D snd_hda_codec_read(codec, - WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_READ, 0); + chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, + &stream_offset, false); =20 if (stream_offset !=3D 0xff) break; @@ -7863,12 +7912,7 @@ static void ae5_post_dsp_param_setup(struct hda_code= c *codec) snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); =20 - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); + chipio_8051_write_exram(codec, 0xfa92, 0x22, true); } =20 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) @@ -8134,12 +8178,7 @@ static void ae7_post_dsp_asi_setup(struct hda_codec = *codec) chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); =20 - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); + chipio_8051_write_exram(codec, 0xfa92, 0x22, true); =20 ae7_post_dsp_pll_setup(codec); ae7_post_dsp_asi_stream_setup(codec); @@ -9133,12 +9172,7 @@ static void r3d_pre_dsp_setup(struct hda_codec *code= c) { chipio_write(codec, 0x18b0a4, 0x000000c2); =20 - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); + chipio_8051_write_exram(codec, 0x1c1e, 0x5b, true); =20 snd_hda_codec_write(codec, 0x11, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); @@ -9148,21 +9182,9 @@ static void r3di_pre_dsp_setup(struct hda_codec *cod= ec) { chipio_write(codec, 0x18b0a4, 0x000000c2); =20 - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); - - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); + chipio_8051_write_exram(codec, 0x1c1e, 0x5b, true); + chipio_8051_write_exram(codec, 0x1920, 0x00, true); + chipio_8051_write_exram(codec, 0x1921, 0x40, true); =20 snd_hda_codec_write(codec, 0x11, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); --=20 2.25.1 From nobody Sat May 10 02:37:35 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; 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[71.65.111.223]) by smtp.googlemail.com with ESMTPSA id l1sm16018572qkj.101.2020.12.08.13.26.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Dec 2020 13:26:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5PCbjvvYW/oUAsYYOiPy2B4hqPD9ZQRXM+oW07hVjwA=; b=afjC1iOzovubWp/4GQ6Js/bxDK26SXI/xXVR0oRDqr0Mo2EDWPCYZvIlMEllYppM4l ItJSZTeHzQ93wH+bIMciFnB3UoLkr96n8e4JPiFWzVx7vcdpmt/asHFBpyHB031JVsi5 dEcLvak53J65PXE64Nsi6bxQ8jzcw8LVrhsjzzByUV2XNp6qo0im4Buwv64BrPZUECWK L0x45vEV60JJVknIAZVIZPg361t4kxl7vO1TWnOIMAJ6zy/J5KFJjlfrzybmTN8VMwwM 1iiQyEC2pXpn9evqDtJVYRtMY+zNWNIaPA2bVIyzp3T60aU97UEYM5UBn32HJGc77CB+ jRKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5PCbjvvYW/oUAsYYOiPy2B4hqPD9ZQRXM+oW07hVjwA=; b=egK/45U5xzINlzrK2Sfg5R8InoOIPSt7ohM0RDSanTltx/78KS9Fn1SrVylcs1g56O xApdpEEwt4Hu7lMocCagYkJZK6UbxdSz4iLdg53BFd4bw4ROu8Thl7jRbbSBd3PUejfZ s/3RIQr/QakMTRPL0ej2+Cc2noV0I+KaRmGotMlfCcWqaTqRL2LBoIun7BHHvv7jvA/k TdaTgfsPDVUEmVfcb9sXkHVa21syZwvXzAmvrwukdEf3X0mfqrhjIn4VKc67zgdSGegO gtrii0i9dQW1Y/k2Odmc40A6/m+Px/YW2DVhodQxYg7CBktS3278Rr4YAF7Z5cbS4mKE fetQ== X-Gm-Message-State: AOAM532Gt8NwE6aZG5pPgjqaSczTIve4aqibHqp9v9ZCNiivDFA5EZxT GojWq8iP6v4aDOyCQtij5Vk= X-Google-Smtp-Source: ABdhPJyjVSHmpo5gLI6FJWP4ooNOPOrImuORRUjA4iuULRciIA1urWMySFLMMWYv6if89rwkIkrGHg== X-Received: by 2002:a37:8341:: with SMTP id f62mr16278527qkd.93.1607462787590; Tue, 08 Dec 2020 13:26:27 -0800 (PST) From: Connor McAdams Cc: conmanx360@gmail.com, Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] ALSA: hda/ca0132 - Ensure DSP is properly setup post-firmware download. Date: Tue, 8 Dec 2020 16:25:44 -0500 Message-Id: <20201208212546.428392-5-conmanx360@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208212546.428392-1-conmanx360@gmail.com> References: <20201208212546.428392-1-conmanx360@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Make sure that the DSP has no DMA channels allocated once the firmware is downloaded, and that the default audio streams in use by the DSP are setup in the correct order. Signed-off-by: Connor McAdams --- sound/pci/hda/patch_ca0132.c | 127 +++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index cb725586d38b..12fee1146fc2 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -1863,6 +1863,27 @@ static void chipio_set_stream_control(struct hda_cod= ec *codec, CONTROL_PARAM_STREAM_CONTROL, enable); } =20 +/* + * Get ChipIO audio stream's status. + */ +static void chipio_get_stream_control(struct hda_codec *codec, + int streamid, unsigned int *enable, + bool use_mutex) +{ + struct ca0132_spec *spec =3D codec->spec; + + if (use_mutex) + mutex_lock(&spec->chipio_mutex); + + chipio_set_control_param_no_mutex(codec, + CONTROL_PARAM_STREAM_ID, streamid); + *enable =3D snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_PARAM_GET, + CONTROL_PARAM_STREAM_CONTROL); + + if (use_mutex) + mutex_unlock(&spec->chipio_mutex); +} =20 /* * Set sampling rate of the connection point. NO MUTEX. @@ -7514,6 +7535,108 @@ static void ca0132_refresh_widget_caps(struct hda_c= odec *codec) } } =20 + +/* If there is an active channel for some reason, find it and free it. */ +static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec) +{ + unsigned int i, tmp; + int status; + + /* Read active DSPDMAC channel register. */ + status =3D chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp); + if (status >=3D 0) { + /* AND against 0xfff to get the active channel bits. */ + tmp =3D tmp & 0xfff; + + /* If there are no active channels, nothing to free. */ + if (!tmp) + return; + } else { + codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n", + __func__); + return; + } + + /* + * Check each DSP DMA channel for activity, and if the channel is + * active, free it. + */ + for (i =3D 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) { + if (dsp_is_dma_active(codec, i)) { + status =3D dspio_free_dma_chan(codec, i); + if (status < 0) + codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n", + __func__, i); + } + } +} + +/* + * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in + * use, audio is no longer routed directly to the DAC/ADC from the HDA str= eam. + * Instead, audio is now routed through the DSP's DMA controllers, which + * the DSP is tasked with setting up itself. Through debugging, it seems t= he + * cause of most of the no-audio on startup issues were due to improperly + * configured DSP DMA channels. + * + * Normally, the DSP configures these the first time an HDA audio stream is + * started post DSP firmware download. That is why creating a 'dummy' stre= am + * worked in fixing the audio in some cases. This works most of the time, = but + * sometimes if a stream is started/stopped before the DSP can setup the D= MA + * configuration registers, it ends up in a broken state. Issues can also + * arise if streams are started in an unusual order, i.e the audio output = dma + * channel being sandwiched between the mic1 and mic2 dma channels. + * + * The solution to this is to make sure that the DSP has no DMA channels + * in use post DSP firmware download, and then to manually start each defa= ult + * DSP stream that uses the DMA channels. These are 0x0c, the audio output + * stream, 0x03, analog mic 1, and 0x04, analog mic 2. + */ +static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec) +{ + const unsigned int dsp_dma_stream_ids[] =3D { 0x0c, 0x03, 0x04 }; + struct ca0132_spec *spec =3D codec->spec; + unsigned int i, tmp; + + /* + * Check if any of the default streams are active, and if they are, + * stop them. + */ + for (i =3D 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { + chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp, + true); + + if (tmp) { + mutex_lock(&spec->chipio_mutex); + chipio_set_stream_control(codec, + dsp_dma_stream_ids[i], 0); + mutex_unlock(&spec->chipio_mutex); + } + } + + /* + * If all DSP streams are inactive, there should be no active DSP DMA + * channels. Check and make sure this is the case, and if it isn't, + * free any active channels. + */ + ca0132_alt_free_active_dma_channels(codec); + + mutex_lock(&spec->chipio_mutex); + + /* Make sure stream 0x0c is six channels. */ + chipio_set_stream_channels(codec, 0x0c, 6); + + for (i =3D 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { + chipio_set_stream_control(codec, + dsp_dma_stream_ids[i], 1); + + /* Give the DSP some time to setup the DMA channel. */ + msleep(75); + } + + mutex_unlock(&spec->chipio_mutex); +} + /* * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio * router', where each entry represents a 48khz audio channel, with a form= at @@ -8251,6 +8374,7 @@ static void r3d_setup_defaults(struct hda_codec *code= c) =20 ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); + ca0132_alt_start_dsp_audio_streams(codec); =20 /*remove DSP headroom*/ tmp =3D FLOAT_ZERO; @@ -8301,6 +8425,7 @@ static void sbz_setup_defaults(struct hda_codec *code= c) =20 ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); + ca0132_alt_start_dsp_audio_streams(codec); sbz_connect_streams(codec); sbz_chipio_startup_data(codec); =20 @@ -8360,6 +8485,7 @@ static void ae5_setup_defaults(struct hda_codec *code= c) =20 ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); + ca0132_alt_start_dsp_audio_streams(codec); chipio_set_stream_control(codec, 0x03, 1); chipio_set_stream_control(codec, 0x04, 1); =20 @@ -8429,6 +8555,7 @@ static void ae7_setup_defaults(struct hda_codec *code= c) =20 ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); + ca0132_alt_start_dsp_audio_streams(codec); ae7_post_dsp_setup_ports(codec); =20 tmp =3D FLOAT_ZERO; --=20 2.25.1 From nobody Sat May 10 02:37:35 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607462874; cv=none; d=zohomail.com; s=zohoarc; b=GVl+RWmezUuF+iBOyb6JR8bnpwS9iLTC6G52mcooo7gdHvTUIsufQ6znqSs/3jyYAy05yoSMOXywhxTZjrIddSjGLhxNxbZOxOLz4PC/yMYyRjHLnps+ID11YsmPXNUKNEzELkE0jjkBsk6fwuMYVWZa3ays3D0z6itFIlDNpeY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607462874; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=5T57w/qT81E5tyEXIT6CUDXHzkp5L3rDJHbJUoKO/vI=; b=ePBN7U+jyGMY0x/qmaZBQ3PPLruYJvBUi1OrBqLodNyEy2kb4Tudlgio+bK3q4B6Cc37bX8Y3izdE1G1sCIowMlpV4Z1A2oouOTCWxgmAtySeIByeexXnXDAX34ZERhine+5gZYcFbL3OALH6GA6GZmRSN9TMYgsvwNT0BxMSVw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1607462874090426.3165389895888; Tue, 8 Dec 2020 13:27:54 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729896AbgLHV1P (ORCPT ); Tue, 8 Dec 2020 16:27:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729855AbgLHV1K (ORCPT ); Tue, 8 Dec 2020 16:27:10 -0500 Received: from mail-qk1-x735.google.com (mail-qk1-x735.google.com [IPv6:2607:f8b0:4864:20::735]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 726A6C0617A6 for ; Tue, 8 Dec 2020 13:26:30 -0800 (PST) Received: by mail-qk1-x735.google.com with SMTP id q5so34113qkc.12 for ; Tue, 08 Dec 2020 13:26:30 -0800 (PST) Received: from localhost.localdomain (cpe-71-65-111-223.cinci.res.rr.com. [71.65.111.223]) by smtp.googlemail.com with ESMTPSA id l1sm16018572qkj.101.2020.12.08.13.26.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Dec 2020 13:26:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5T57w/qT81E5tyEXIT6CUDXHzkp5L3rDJHbJUoKO/vI=; b=nin7QQE8YNSUVSu84uCpoXp1R15OKl9fltBiJlL6TZtuRypvuwO5Mo9xCF995wOZiQ v+BXxdtv22nZthrgpbSwrmFZ4hL3QxJpP2Ff7/QsuUVe2kSRIY33RIZ8h0tXEtWsAP6r jI3OovhQ5oD0szjBrZoJAIUv045KYigepNhwDSkFuVIWKU0zf2KJ/mz4vx5zezOFZ7/h kLPLlky81k9ctsv5YeRdMeOJmfXkx0V+Btes5AYmy0d4zt/ag7Ra8jzwEn0IKITa6me2 1+2zi6VgyjPicycho7OPCNmemWLVQBhkP86ZwNrsiy7cAJQgP7ZdZDKPuKAlpNLNqcVo Cm4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5T57w/qT81E5tyEXIT6CUDXHzkp5L3rDJHbJUoKO/vI=; b=WJwe3TxKalHP9GJ2Ddb7nAeyXTy3K5DzBORLIKx6GHVAskXhwMw1dlXtPIoK+GBptC DsJCSTzoctsWc7+uzL8qF2ylKE+B+KnqN0/cBoSJcbYJO1ADWqa/8yylcXhzZcm9WjC7 4wmofYV1q7x9ruIsh4TuT3dXleWx6JrMMAIXQhg4kVw2p7TM0JvV0MLMFWJ3gFVewtoA K8284+G6LZBdkL7eu+jGpv+YhHRB0H5lWGeDIU3eBFZiGkAaVMPeEIFIhrs5ggAMiWDK hdot9NmeC2gOhF25c6ibg+8pSXW2yBtpqfbW6pk13uYKsZKteNAKwFkWWsFrhPFbLQI5 2jYw== X-Gm-Message-State: AOAM533reAOFgPiAumCmrlbnyCUHljm4UfMIU5PslWr39FaHz8FrrX0A E8sKldQCFrNQzf44tI1ljgw= X-Google-Smtp-Source: ABdhPJwV5YYMsgKMW72bv3/4FPhTpA7TfyNdCpvDfxPOriMWl/UN7+6dXkeu+dGgp4KeeOwH1KT6XA== X-Received: by 2002:a37:a5d5:: with SMTP id o204mr33904190qke.112.1607462789674; Tue, 08 Dec 2020 13:26:29 -0800 (PST) From: Connor McAdams Cc: conmanx360@gmail.com, Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] ALSA: hda/ca0132 - Remove now unnecessary DSP setup functions. Date: Tue, 8 Dec 2020 16:25:45 -0500 Message-Id: <20201208212546.428392-6-conmanx360@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208212546.428392-1-conmanx360@gmail.com> References: <20201208212546.428392-1-conmanx360@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Now that the DSP's audio configuration is understood, remove previous hacky methods of trying to properly configure it. Signed-off-by: Connor McAdams --- sound/pci/hda/patch_ca0132.c | 105 ----------------------------------- 1 file changed, 105 deletions(-) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 12fee1146fc2..b7d36c9b28b5 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -2436,13 +2436,6 @@ static int dspio_set_uint_param(struct hda_codec *co= dec, int mod_id, sizeof(unsigned int)); } =20 -static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod= _id, - int req, const unsigned int data) -{ - return dspio_set_param(codec, mod_id, 0x00, req, &data, - sizeof(unsigned int)); -} - /* * Allocate a DSP DMA channel via an SCP message */ @@ -7789,24 +7782,6 @@ static void ca0132_alt_init_speaker_tuning(struct hd= a_codec *codec) SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); } =20 -/* - * Creates a dummy stream to bind the output to. This seems to have to be = done - * after changing the main outputs source and destination streams. - */ -static void ca0132_alt_create_dummy_stream(struct hda_codec *codec) -{ - struct ca0132_spec *spec =3D codec->spec; - unsigned int stream_format; - - stream_format =3D snd_hdac_calc_stream_format(48000, 2, - SNDRV_PCM_FORMAT_S32_LE, 32, 0); - - snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, - 0, stream_format); - - snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); -} - /* * Initialize mic for non-chromebook ca0132 implementations. */ @@ -7848,9 +7823,6 @@ static void sbz_connect_streams(struct hda_codec *cod= ec) =20 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); =20 - chipio_set_stream_channels(codec, 0x0C, 6); - chipio_set_stream_control(codec, 0x0C, 1); - /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ chipio_write_no_mutex(codec, 0x18a020, 0x00000043); =20 @@ -7898,9 +7870,6 @@ static void sbz_chipio_startup_data(struct hda_codec = *codec) break; } =20 - chipio_set_stream_channels(codec, 0x0c, 6); - chipio_set_stream_control(codec, 0x0c, 1); - if (dsp_out_remap_data) chipio_remap_stream(codec, dsp_out_remap_data); =20 @@ -7908,57 +7877,6 @@ static void sbz_chipio_startup_data(struct hda_codec= *codec) mutex_unlock(&spec->chipio_mutex); } =20 -/* - * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. Th= is is - * done after the DSP is loaded. - */ -static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec) -{ - struct ca0132_spec *spec =3D codec->spec; - unsigned int tmp, i; - - /* - * Gotta run these twice, or else mic works inconsistently. Not clear - * why this is, but multiple tests have confirmed it. - */ - for (i =3D 0; i < 2; i++) { - switch (ca0132_quirk(spec)) { - case QUIRK_SBZ: - case QUIRK_AE5: - case QUIRK_AE7: - tmp =3D 0x00000003; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - tmp =3D 0x00000000; - dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); - tmp =3D 0x00000001; - dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); - tmp =3D 0x00000004; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - tmp =3D 0x00000005; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - tmp =3D 0x00000000; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - break; - case QUIRK_R3D: - case QUIRK_R3DI: - tmp =3D 0x00000000; - dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); - tmp =3D 0x00000001; - dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); - tmp =3D 0x00000004; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - tmp =3D 0x00000005; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - tmp =3D 0x00000000; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - break; - default: - break; - } - msleep(100); - } -} - static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) { struct ca0132_spec *spec =3D codec->spec; @@ -8076,9 +7994,6 @@ static void ae5_post_dsp_stream_setup(struct hda_code= c *codec) =20 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); =20 - chipio_set_stream_channels(codec, 0x0C, 6); - chipio_set_stream_control(codec, 0x0C, 1); - chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); =20 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); @@ -8136,9 +8051,6 @@ static void ae7_post_dsp_setup_ports(struct hda_codec= *codec) =20 mutex_lock(&spec->chipio_mutex); =20 - chipio_set_stream_channels(codec, 0x0c, 6); - chipio_set_stream_control(codec, 0x0c, 1); - /* Seems to share the same port remapping as the SBZ. */ chipio_remap_stream(codec, &stream_remap_data[1]); =20 @@ -8164,8 +8076,6 @@ static void ae7_post_dsp_asi_stream_setup(struct hda_= codec *codec) ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); =20 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); - chipio_set_stream_channels(codec, 0x0c, 6); - chipio_set_stream_control(codec, 0x0c, 1); =20 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); @@ -8372,7 +8282,6 @@ static void r3d_setup_defaults(struct hda_codec *code= c) if (spec->dsp_state !=3D DSP_DOWNLOADED) return; =20 - ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); =20 @@ -8423,15 +8332,11 @@ static void sbz_setup_defaults(struct hda_codec *co= dec) if (spec->dsp_state !=3D DSP_DOWNLOADED) return; =20 - ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); sbz_connect_streams(codec); sbz_chipio_startup_data(codec); =20 - chipio_set_stream_control(codec, 0x03, 1); - chipio_set_stream_control(codec, 0x04, 1); - /* * Sets internal input loopback to off, used to have a switch to * enable input loopback, but turned out to be way too buggy. @@ -8466,8 +8371,6 @@ static void sbz_setup_defaults(struct hda_codec *code= c) } =20 ca0132_alt_init_speaker_tuning(codec); - - ca0132_alt_create_dummy_stream(codec); } =20 /* @@ -8483,11 +8386,8 @@ static void ae5_setup_defaults(struct hda_codec *cod= ec) if (spec->dsp_state !=3D DSP_DOWNLOADED) return; =20 - ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); - chipio_set_stream_control(codec, 0x03, 1); - chipio_set_stream_control(codec, 0x04, 1); =20 /* New, unknown SCP req's */ tmp =3D FLOAT_ZERO; @@ -8536,8 +8436,6 @@ static void ae5_setup_defaults(struct hda_codec *code= c) } =20 ca0132_alt_init_speaker_tuning(codec); - - ca0132_alt_create_dummy_stream(codec); } =20 /* @@ -8553,7 +8451,6 @@ static void ae7_setup_defaults(struct hda_codec *code= c) if (spec->dsp_state !=3D DSP_DOWNLOADED) return; =20 - ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); ae7_post_dsp_setup_ports(codec); @@ -8622,8 +8519,6 @@ static void ae7_setup_defaults(struct hda_codec *code= c) } =20 ca0132_alt_init_speaker_tuning(codec); - - ca0132_alt_create_dummy_stream(codec); } =20 /* --=20 2.25.1