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[71.65.111.223]) by smtp.googlemail.com with ESMTPSA id d190sm3852290qkf.112.2020.12.10.08.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 08:07:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IaJnWNUybnDRToq59E44bnvu+Jic0mLbhcwyhGMTzRg=; b=g+mxm6coxLYmTo9xcwa8YCqTf/r9WRXpwm6Kb9H8g1fxJKcJ+6wVd6LcC1oLcPdWnI +qcmDfv8DiB7ePiicz6BLJknwjPytnPnm2coOvXjjnawdOi1wyGON0jUX9MvyKW0dFAl ziPlFGzz82SC4HA8wvHPWFltP23SbL0PO3CM3XmgbLPnq8Yo8J7UAEJdAWgViMgkDawX wlrRIzLZZeHfdFgGDy1Dq3LloFvc8nV8WyO8XsalHLPj+9olE+Hi8gSpWJ5Nqi3hmbHl UTEbfjNQIVcYYevJIZ9m6EV4a2Uym+Fsnm7ICg2WkCDm0iE91xVIxBcziQPIVgEOhNrA 1rZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IaJnWNUybnDRToq59E44bnvu+Jic0mLbhcwyhGMTzRg=; b=hJgAt5576Xqav9WQZtRwM53T1CenqyccXeN1v9NSpBU6RYgq0SKQy5LsWA5eloxWXZ N/vLUSN7kVFwuOI0mBjqrtZ44lrxMB7LE07K5g+bwZ/OEOvf7H9ynEaNVIezGL5HGPer Iiz/cJig5/CKxb11Oan7VcDJWNbHOJYs/fTkicJG+wTndAq6uLD3qZPvStsEnKCWVdHV 5+jgLcwb3nDRxM5cqK7P3aWCmt9viHtCcgDbrh4iPn5JMT3CTgEfa+oQDxo/8u4+2bdh C3B0f1izPZbJvPpLpvfem+pm83fUIRMsehTnFvYk3fnOZDaAOreSs5/CziIK6lbRlqV3 JN9w== X-Gm-Message-State: AOAM530sckoIZrYkxWZxHuzmEqWR8k9km2gyTduD+t6Tbo6CXZHAZM5M lPFSJWEd9mPlmfKCIL3K9rc= X-Google-Smtp-Source: ABdhPJy9R5XGjJibBGGyFMY5hnkxdoG/RC/758l2eEMy+43kGHS2+NHDuMYDV/BPfzWhOFMlkRvFcQ== X-Received: by 2002:ac8:6bc9:: with SMTP id b9mr10135474qtt.51.1607616444591; Thu, 10 Dec 2020 08:07:24 -0800 (PST) From: Connor McAdams Cc: conmanx360@gmail.com, Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] ALSA: hda/ca0132 - Reset codec upon initialization. Date: Thu, 10 Dec 2020 11:06:53 -0500 Message-Id: <20201210160658.461739-2-conmanx360@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201210160658.461739-1-conmanx360@gmail.com> References: <20201210160658.461739-1-conmanx360@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Reset the codec upon initialization to clear out anything that may have been setup on a previous boot into Windows, or in case of an improper shutdown. Signed-off-by: Connor McAdams --- sound/pci/hda/patch_ca0132.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 6d647d461eab..7ce4a966b733 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -8642,6 +8642,22 @@ static void ca0132_init_chip(struct hda_codec *codec) =20 mutex_init(&spec->chipio_mutex); =20 + /* + * The Windows driver always does this upon startup, which seems to + * clear out any previous configuration. This should help issues where + * a boot into Windows prior to a boot into Linux breaks things. Also, + * Windows always sends the reset twice. + */ + if (ca0132_use_alt_functions(spec)) { + chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); + chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2); + + snd_hda_codec_write(codec, codec->core.afg, 0, + AC_VERB_SET_CODEC_RESET, 0); + snd_hda_codec_write(codec, codec->core.afg, 0, + AC_VERB_SET_CODEC_RESET, 0); + } + spec->cur_out_type =3D SPEAKER_OUT; if (!ca0132_use_alt_functions(spec)) spec->cur_mic_type =3D DIGITAL_MIC; @@ -9262,11 +9278,6 @@ static void ae5_register_set(struct hda_codec *codec) =20 if (ca0132_quirk(spec) =3D=3D QUIRK_AE5) ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); - - chipio_write(codec, 0x18b0a4, 0x000000c2); - - snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); - snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); } =20 /* --=20 2.25.1 From nobody Sat May 10 02:10:35 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607618219; cv=none; d=zohomail.com; s=zohoarc; b=dqdM3DIBB4hNQPVVZePrKU61EYYl1UIU4bO+gYtmHJYty0Wr72rHhrzpCJdV9F+HnWMHBvGH3IO8fYqnKDf4hP6yz1YQ5v/o/vA2mwNWavTOfYPh51PAnyuXHCZEc4VQlJyl6D6CmLoM9p4wgVJKOS7D/6GrK+8IL+IylvR8vFw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607618219; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=2oxYtLvh9Yue0U2KPaThGLnKUpw3c+yg4zRy4/rBMX8=; b=j8SUoEctuEhFKEPWg4F874cakKkIo7VZwLNfWMmgcGcamgI472JlO+mk2+YFInBizQIMd4Pcqokf+8ctwA/aLbvrkuF4WB/M8dT+JIQE5Nhy7EkHtAdAvuHcEvfLq8COGCr/+u2TJ4TETHPbdFGW+KSblv0wRp1VBNrqVE/OmBw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1607618218939800.7448288389254; Thu, 10 Dec 2020 08:36:58 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392223AbgLJQJd (ORCPT ); Thu, 10 Dec 2020 11:09:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2403826AbgLJQII (ORCPT ); Thu, 10 Dec 2020 11:08:08 -0500 Received: from mail-qk1-x735.google.com (mail-qk1-x735.google.com [IPv6:2607:f8b0:4864:20::735]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DB32C061257 for ; Thu, 10 Dec 2020 08:07:28 -0800 (PST) Received: by mail-qk1-x735.google.com with SMTP id y18so5217426qki.11 for ; Thu, 10 Dec 2020 08:07:28 -0800 (PST) Received: from localhost.localdomain (cpe-71-65-111-223.cinci.res.rr.com. [71.65.111.223]) by smtp.googlemail.com with ESMTPSA id d190sm3852290qkf.112.2020.12.10.08.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 08:07:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2oxYtLvh9Yue0U2KPaThGLnKUpw3c+yg4zRy4/rBMX8=; b=Zyb/5DHbjrR7Ch7/7OaBwqNiElg3vUwd2JpgIltykl27Md56C6oF/JPPPYo8H9t0qg 2g2Rdc2s8GiKVctNIu/2ZvU9q0+ridF8XSKrCu+XYYiXkeOthJWp0fmra+WLhqgKiLq/ ePMql1cEe4pyu46irDV9reiEcwZ3f4Aj+Yd64JyvVTMQ1J+Ff8BMC2i/mPzrC4Fugopm yKoaXMBBVaUqda58oOgkM+3xxUqkm7n8ckfgj8jbt4O4DY8Bq52fQ7FkZ2MIPeNKWQmc yRmrMkIoNxnVFyj5HioVRe2cAjpPZbbWnDHkTLiHdpQpcTC1Sai53saohsj5i1DSZCmM VyAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2oxYtLvh9Yue0U2KPaThGLnKUpw3c+yg4zRy4/rBMX8=; b=DUc6nYbJdIxD/MnP8un0tahoGYpzO1lKr9W9drHtxRQqyWnzL50gqSUgK2nSZg7HK5 6hy3xMVRPDR5apDD+4oq2Eg3KFUc6Pbnc9/hyjwSm2twRi1iSxhO42Lx0vUmjCEnsFHa GbxfSvICxL/onmGh02iNvQYO1TMuMl4w2QjFpKOAAPbDOrNJ3/wW0sbG6RLMONuJ5s8o jql5EJOky7tg8+o3RJ4paOgypTZ0fuhpFaOpAEfoYI93xaIi0frX6Uvd/XCnAwZT0/mf 6TlDk4HY8m+N1X4KLdxVAh0aAzfF5F4r9ojIlYCsAYP6teqRr9YYJinbVT6r9pbHgKMJ Jmyg== X-Gm-Message-State: AOAM531Kwf/wAgl9AjWpzP6s+3jH06MHzNAYz8up4vvTOjki+KB9D7v1 ntzGhE5ormOqp3eHeUxJUIk= X-Google-Smtp-Source: ABdhPJxddCr4bSAa3u5FbtvZhI2Vx5MUW0HXnCcEFp3E9sbGUNPCC6lBTig95GvK+hyHfnlWZhWNGw== X-Received: by 2002:a37:a917:: with SMTP id s23mr9850874qke.214.1607616447306; Thu, 10 Dec 2020 08:07:27 -0800 (PST) From: Connor McAdams Cc: conmanx360@gmail.com, Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] ALSA: hda/ca0132 - Add stream port remapping function. Date: Thu, 10 Dec 2020 11:06:54 -0500 Message-Id: <20201210160658.461739-3-conmanx360@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201210160658.461739-1-conmanx360@gmail.com> References: <20201210160658.461739-1-conmanx360@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add function for remapping a ChipIO stream's ports. Also include some documentation as to how this works. Signed-off-by: Connor McAdams --- sound/pci/hda/patch_ca0132.c | 208 ++++++++++++++++++++++++++--------- 1 file changed, 156 insertions(+), 52 deletions(-) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 7ce4a966b733..8d2f12f2ce3f 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -788,6 +788,40 @@ static const struct ae5_filter_set ae5_filter_presets[= ] =3D { } }; =20 +/* + * Data structures for storing audio router remapping data. These are used= to + * remap a currently active streams ports. + */ +struct chipio_stream_remap_data { + unsigned int stream_id; + unsigned int count; + + unsigned int offset[16]; + unsigned int value[16]; +}; + +static const struct chipio_stream_remap_data stream_remap_data[] =3D { + { .stream_id =3D 0x14, + .count =3D 0x04, + .offset =3D { 0x00, 0x04, 0x08, 0x0c }, + .value =3D { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 }, + }, + { .stream_id =3D 0x0c, + .count =3D 0x0c, + .offset =3D { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, + 0x20, 0x24, 0x28, 0x2c }, + .value =3D { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, + 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7, + 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb }, + }, + { .stream_id =3D 0x0c, + .count =3D 0x08, + .offset =3D { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c }, + .value =3D { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5, + 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb }, + } +}; + enum hda_cmd_vendor_io { /* for DspIO node */ VENDOR_DSPIO_SCP_WRITE_DATA_LOW =3D 0x000, @@ -7423,6 +7457,104 @@ static void ca0132_refresh_widget_caps(struct hda_c= odec *codec) } } =20 +/* + * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio + * router', where each entry represents a 48khz audio channel, with a form= at + * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number + * value. The 2-bit number value is seemingly 0 if inactive, 1 if active, + * and 3 if it's using Sample Rate Converter ports. + * An example is: + * 0x0001f8c0 + * In this case, f8 is the destination, and c0 is the source. The number v= alue + * is 1. + * This region of memory is normally managed internally by the 8051, where + * the region of exram memory from 0x1477-0x1575 has each byte represent an + * entry within the 0x190000 range, and when a range of entries is in use,= the + * ending value is overwritten with 0xff. + * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO + * streamID's, where each entry is a starting 0x190000 port offset. + * 0x159d in exram is the same as 0x1578, except it contains the ending po= rt + * offset for the corresponding streamID. + * + * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by + * the 8051, then manually overwritten to remap the ports to work with the + * new DACs. + * + * Currently known portID's: + * 0x00-0x1f: HDA audio stream input/output ports. + * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to + * have the lower-nibble set to 0x1, 0x2, and 0x9. + * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned. + * 0xe0-0xff: DAC/ADC audio input/output ports. + * + * Currently known streamID's: + * 0x03: Mic1 ADC to DSP. + * 0x04: Mic2 ADC to DSP. + * 0x05: HDA node 0x02 audio stream to DSP. + * 0x0f: DSP Mic exit to HDA node 0x07. + * 0x0c: DSP processed audio to DACs. + * 0x14: DAC0, front L/R. + * + * It is possible to route the HDA audio streams directly to the DAC and + * bypass the DSP entirely, with the only downside being that since the DSP + * does volume control, the only volume control you'll get is through PCM = on + * the PC side, in the same way volume is handled for optical out. This ma= y be + * useful for debugging. + */ +static void chipio_remap_stream(struct hda_codec *codec, + const struct chipio_stream_remap_data *remap_data) +{ + unsigned int i, stream_offset, tmp; + + /* Get the starting port for the stream to be remapped. */ + tmp =3D 0x1578 + remap_data->stream_id; + for (i =3D 0; i < 2; i++) { + snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_ADDRESS_LOW + i, + ((tmp >> (i * 8)) & 0xff)); + } + + stream_offset =3D snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_DATA_READ, 0); + + /* + * Check if the stream's port value is 0xff, because the 8051 may not + * have gotten around to setting up the stream yet. Wait until it's + * setup to remap it's ports. + */ + if (stream_offset =3D=3D 0xff) { + for (i =3D 0; i < 5; i++) { + msleep(25); + + stream_offset =3D snd_hda_codec_read(codec, + WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_DATA_READ, 0); + + if (stream_offset !=3D 0xff) + break; + } + } + + if (stream_offset =3D=3D 0xff) { + codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap faile= d!\n", + __func__, remap_data->stream_id); + return; + } + + /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */ + stream_offset *=3D 0x04; + stream_offset +=3D 0x190000; + + for (i =3D 0; i < remap_data->count; i++) { + chipio_write_no_mutex(codec, + stream_offset + remap_data->offset[i], + remap_data->value[i]); + } + + /* Update stream map configuration. */ + chipio_write_no_mutex(codec, 0x19042c, 0x00000001); +} + /* * Default speaker tuning values setup for alternative codecs. */ @@ -7570,46 +7702,35 @@ static void sbz_connect_streams(struct hda_codec *c= odec) */ static void sbz_chipio_startup_data(struct hda_codec *codec) { + const struct chipio_stream_remap_data *dsp_out_remap_data; struct ca0132_spec *spec =3D codec->spec; =20 mutex_lock(&spec->chipio_mutex); codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); =20 - /* These control audio output */ - chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); - chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); - chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); - chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); - /* Signal to update I think */ - chipio_write_no_mutex(codec, 0x19042c, 0x00000001); + /* Remap DAC0's output ports. */ + chipio_remap_stream(codec, &stream_remap_data[0]); =20 - chipio_set_stream_channels(codec, 0x0C, 6); - chipio_set_stream_control(codec, 0x0C, 1); - /* No clue what these control */ - if (ca0132_quirk(spec) =3D=3D QUIRK_SBZ) { - chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); - chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); - chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); - chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); - chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); - chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); - chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); - chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); - chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); - chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); - chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); - chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); - } else if (ca0132_quirk(spec) =3D=3D QUIRK_ZXR) { - chipio_write_no_mutex(codec, 0x190038, 0x000140c2); - chipio_write_no_mutex(codec, 0x19003c, 0x000141c3); - chipio_write_no_mutex(codec, 0x190040, 0x000150c4); - chipio_write_no_mutex(codec, 0x190044, 0x000151c5); - chipio_write_no_mutex(codec, 0x190050, 0x000142c8); - chipio_write_no_mutex(codec, 0x190054, 0x000143c9); - chipio_write_no_mutex(codec, 0x190058, 0x000152ca); - chipio_write_no_mutex(codec, 0x19005c, 0x000153cb); + /* Remap DSP audio output stream ports. */ + switch (ca0132_quirk(spec)) { + case QUIRK_SBZ: + dsp_out_remap_data =3D &stream_remap_data[1]; + break; + + case QUIRK_ZXR: + dsp_out_remap_data =3D &stream_remap_data[2]; + break; + + default: + dsp_out_remap_data =3D NULL; + break; } - chipio_write_no_mutex(codec, 0x19042c, 0x00000001); + + chipio_set_stream_channels(codec, 0x0c, 6); + chipio_set_stream_control(codec, 0x0c, 1); + + if (dsp_out_remap_data) + chipio_remap_stream(codec, dsp_out_remap_data); =20 codec_dbg(codec, "Startup Data exited, mutex released.\n"); mutex_unlock(&spec->chipio_mutex); @@ -7842,34 +7963,17 @@ static void ae5_post_dsp_startup_data(struct hda_co= dec *codec) mutex_unlock(&spec->chipio_mutex); } =20 -static const unsigned int ae7_port_set_data[] =3D { - 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 0x0001e2c4, 0x0001e3c5, - 0x0001e8c6, 0x0001e9c7, 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb -}; - static void ae7_post_dsp_setup_ports(struct hda_codec *codec) { struct ca0132_spec *spec =3D codec->spec; - unsigned int i, count, addr; =20 mutex_lock(&spec->chipio_mutex); =20 chipio_set_stream_channels(codec, 0x0c, 6); chipio_set_stream_control(codec, 0x0c, 1); =20 - count =3D ARRAY_SIZE(ae7_port_set_data); - addr =3D 0x190030; - for (i =3D 0; i < count; i++) { - chipio_write_no_mutex(codec, addr, ae7_port_set_data[i]); - - /* Addresses are incremented by 4-bytes. */ - addr +=3D 0x04; - } - - /* - * Port setting always ends with a write of 0x1 to address 0x19042c. - */ - chipio_write_no_mutex(codec, 0x19042c, 0x00000001); + /* Seems to share the same port remapping as the SBZ. */ + chipio_remap_stream(codec, &stream_remap_data[1]); =20 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); --=20 2.25.1 From nobody Sat May 10 02:10:35 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; 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[71.65.111.223]) by smtp.googlemail.com with ESMTPSA id d190sm3852290qkf.112.2020.12.10.08.07.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 08:07:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LNFp0e1oxBHLLAbT98jciqioJbJK5/HPHacwl39pCE4=; b=IxVDdTJOW62Ph/K7eG/YCffUU8ua98VD/E4CYuBqyyVt7m3Voea7EXFrTgosgE/9z4 /JQLQjl6ZY3G8yXIPrxlg1CgHcptQYV52P84VVy1rdohFoDD3ZSLR9MpHbYrzYQYAikP QZYxj0aqMaWGVbQFhXydxf9J5+wzqOgG/MtEvrotEwYvUj4LSoJ7scMf4wjrmpGaogew 2KMGA1jzgE3Vl4f1MowYPriISWa6iYNB/Ef/UDKvu66dvNgRD2DPa+z6gHpLWQnaTK6K FSp+hub37+dJNSNlBKOj+XtS8j0cnq90BypmsLF7F9wbkUNs7cPlxQqBt5hwwSEHnNp2 cB1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LNFp0e1oxBHLLAbT98jciqioJbJK5/HPHacwl39pCE4=; b=L6zXXxsEm5hHq2oiLLB15Id9iPUYURUqqoy69oPw5dve0LIKZ1fsKcoPdOfznHvqkL QQ1oRBDp6BHyww/RCGqk8RsJy9N9RAmNz++Q2tk1KalxaXrvMGhf/iClK0VA4ado6oin hCOCQaoEXTd2awvxqCcAlpLlfA5ODtb97L4i+D+2kTv48TJ2rH1Djxv4ldQZjP1jAu+K llA6iqmh6geSO8N5wMvXw9ac/fNryGe2CRC88oO+iHCz68eK2RXeRFc6cjbsMrL5Sfu1 njoc+d5VcT7O9yeS/32DamqHn3DF2EO9KgEoc8Ts42r8Ud+8BXhWdfwhvDHmyibanT4b GSrg== X-Gm-Message-State: AOAM531pALJc8jydNQxOM+DtObFc6Af/wFs7oHLV+2jvO8gq1Zy1/NBX Cm0fe4NtpI0K10opTMR6CG/OnM2yHcw= X-Google-Smtp-Source: ABdhPJw+IGq515hstY9rhetdhZePZmALzlL0Q61eB2u/VgWWVO75b1vkxRAlVIEb95nZKaa7z7rD6Q== X-Received: by 2002:a05:622a:109:: with SMTP id u9mr9773412qtw.213.1607616449508; Thu, 10 Dec 2020 08:07:29 -0800 (PST) From: Connor McAdams Cc: conmanx360@gmail.com, Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] ALSA: hda/ca0132 - Add 8051 exram helper functions. Date: Thu, 10 Dec 2020 11:06:55 -0500 Message-Id: <20201210160658.461739-4-conmanx360@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201210160658.461739-1-conmanx360@gmail.com> References: <20201210160658.461739-1-conmanx360@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add functions for both reading and writing to the 8051's exram. Also, add a little bit of documentation on how the addresses are segmented. Signed-off-by: Connor McAdams --- sound/pci/hda/patch_ca0132.c | 137 ++++++++++++++++++++--------------- 1 file changed, 79 insertions(+), 58 deletions(-) v2 changes: -Remove conditional mutex. diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 8d2f12f2ce3f..f84815cc8d2f 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -1901,6 +1901,70 @@ static void chipio_8051_write_direct(struct hda_code= c *codec, snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); } =20 +/* + * Writes to the 8051's exram, which has 16-bits of address space. + * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff. + * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by + * setting the pmem bank selection SFR. + * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xff= ff + * being writable. + */ +static void chipio_8051_set_address(struct hda_codec *codec, unsigned int = addr) +{ + unsigned int tmp; + + /* Lower 8-bits. */ + tmp =3D addr & 0xff; + snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); + + /* Upper 8-bits. */ + tmp =3D (addr >> 8) & 0xff; + snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); +} + +static void chipio_8051_set_data(struct hda_codec *codec, unsigned int dat= a) +{ + /* 8-bits of data. */ + snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff); +} + +static unsigned int chipio_8051_get_data(struct hda_codec *codec) +{ + return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_8051_DATA_READ, 0); +} + +static void chipio_8051_write_exram(struct hda_codec *codec, + unsigned int addr, unsigned int data) +{ + struct ca0132_spec *spec =3D codec->spec; + + mutex_lock(&spec->chipio_mutex); + + chipio_8051_set_address(codec, addr); + chipio_8051_set_data(codec, data); + + mutex_unlock(&spec->chipio_mutex); +} + +static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec, + unsigned int addr, unsigned int data) +{ + chipio_8051_set_address(codec, addr); + chipio_8051_set_data(codec, data); +} + +/* Readback data from the 8051's exram. No mutex. */ +static void chipio_8051_read_exram(struct hda_codec *codec, + unsigned int addr, unsigned int *data) +{ + chipio_8051_set_address(codec, addr); + *data =3D chipio_8051_get_data(codec); +} + /* * Enable clocks. */ @@ -7422,18 +7486,10 @@ static void ca0132_init_analog_mic2(struct hda_code= c *codec) struct ca0132_spec *spec =3D codec->spec; =20 mutex_lock(&spec->chipio_mutex); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); + + chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00); + chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00); + mutex_unlock(&spec->chipio_mutex); } =20 @@ -7504,18 +7560,11 @@ static void ca0132_refresh_widget_caps(struct hda_c= odec *codec) static void chipio_remap_stream(struct hda_codec *codec, const struct chipio_stream_remap_data *remap_data) { - unsigned int i, stream_offset, tmp; + unsigned int i, stream_offset; =20 /* Get the starting port for the stream to be remapped. */ - tmp =3D 0x1578 + remap_data->stream_id; - for (i =3D 0; i < 2; i++) { - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW + i, - ((tmp >> (i * 8)) & 0xff)); - } - - stream_offset =3D snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_READ, 0); + chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, + &stream_offset); =20 /* * Check if the stream's port value is 0xff, because the 8051 may not @@ -7526,9 +7575,8 @@ static void chipio_remap_stream(struct hda_codec *cod= ec, for (i =3D 0; i < 5; i++) { msleep(25); =20 - stream_offset =3D snd_hda_codec_read(codec, - WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_READ, 0); + chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, + &stream_offset); =20 if (stream_offset !=3D 0xff) break; @@ -7863,12 +7911,7 @@ static void ae5_post_dsp_param_setup(struct hda_code= c *codec) snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); =20 - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); + chipio_8051_write_exram(codec, 0xfa92, 0x22); } =20 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) @@ -8134,12 +8177,7 @@ static void ae7_post_dsp_asi_setup(struct hda_codec = *codec) chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); =20 - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); + chipio_8051_write_exram(codec, 0xfa92, 0x22); =20 ae7_post_dsp_pll_setup(codec); ae7_post_dsp_asi_stream_setup(codec); @@ -9133,12 +9171,7 @@ static void r3d_pre_dsp_setup(struct hda_codec *code= c) { chipio_write(codec, 0x18b0a4, 0x000000c2); =20 - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); + chipio_8051_write_exram(codec, 0x1c1e, 0x5b); =20 snd_hda_codec_write(codec, 0x11, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); @@ -9148,21 +9181,9 @@ static void r3di_pre_dsp_setup(struct hda_codec *cod= ec) { chipio_write(codec, 0x18b0a4, 0x000000c2); =20 - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); - - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); - snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, - VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); + chipio_8051_write_exram(codec, 0x1c1e, 0x5b); + chipio_8051_write_exram(codec, 0x1920, 0x00); + chipio_8051_write_exram(codec, 0x1921, 0x40); =20 snd_hda_codec_write(codec, 0x11, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); --=20 2.25.1 From nobody Sat May 10 02:10:35 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; 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[71.65.111.223]) by smtp.googlemail.com with ESMTPSA id d190sm3852290qkf.112.2020.12.10.08.07.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 08:07:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8qkH/T0u1gIF+PhxKKFzFehDKE3HDIIdIpQZFLT4Bhs=; b=TTCCXDSLrBA2NXLYRXoh5BMEly9WIUnOfhgx7j16Bglfc5BJz1rjDT2guFKeq43Sof nVG1qWc598tBvGLf1WeHNilHbrG7olVsOOfnNvn5GsHCIimYEgCrgx9N0nH4TZFNYPYj mgPcYASjrHDrb6X7mB1PXUDfVC3xEsJCnGmDrXa+WbH/E7cK63jYEuupVdv36Q/vZWxZ O3GMHCLNAOURheN+L73YIlI+ycmILecTaUYc4Z4Ssp9gec4rldklTehOeEtWeqKscgcJ q8rhKRimXqXWbUwJh0BExMUTEqdUmatmknMb67i+i21ctEM3gs6b1Zf05sVSsKzMsehi Qv1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8qkH/T0u1gIF+PhxKKFzFehDKE3HDIIdIpQZFLT4Bhs=; b=b2rnIBHC5/54n2VNVgR4GK8PUAjIEdhRBycojXR1mcC+XLYJ9+trGPHCGPlDP5ZwWI 5xR/sI8Iksfnf8OzDCiX6gOHB7Om0LcR5zmoKsiKf7WuTvqm/XC5HvLsOXpNzFKflCPF X9J9cTa7m+kNUWdtQgNJxDbcQZWfuK01bU8JvEuGciYFA9ITpkXVQ3xsdDQ/OqTPCIES czzxe/KzikFX6yOtfYSZHlr2iPMESshDoFY7XPH10v7WfYN+SVb6HTgP0dkE+wWtQ7ds skd4t3d0VbPTQRqMqPb+JbxS6ma22pTAe5t9fBJ13U1WJEm27Xi7Z6gcHkg7txxQ6lG1 jibA== X-Gm-Message-State: AOAM530sGLdYZ2RTMLW15UIC7W6VExpAAZyeFFzkdBr8Y6p5P/KR3r6q hSAK6bAIVo/j7uDWl++uFUtIwemqcPk= X-Google-Smtp-Source: ABdhPJxHRY4OBGREbkOnuB7bjpNabJlG4/6RoDaVFn5Y5BgqCwSKYQQBaZu4ESCJPPRaVWshLqRXDg== X-Received: by 2002:a37:aec2:: with SMTP id x185mr10249359qke.64.1607616451795; Thu, 10 Dec 2020 08:07:31 -0800 (PST) From: Connor McAdams Cc: conmanx360@gmail.com, Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] ALSA: hda/ca0132 - Ensure DSP is properly setup post-firmware download. Date: Thu, 10 Dec 2020 11:06:56 -0500 Message-Id: <20201210160658.461739-5-conmanx360@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201210160658.461739-1-conmanx360@gmail.com> References: <20201210160658.461739-1-conmanx360@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Make sure that the DSP has no DMA channels allocated once the firmware is downloaded, and that the default audio streams in use by the DSP are setup in the correct order. Signed-off-by: Connor McAdams --- sound/pci/hda/patch_ca0132.c | 119 +++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) v2 changes: -Remove conditional mutex. diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index f84815cc8d2f..8884ad0910cd 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -1863,6 +1863,18 @@ static void chipio_set_stream_control(struct hda_cod= ec *codec, CONTROL_PARAM_STREAM_CONTROL, enable); } =20 +/* + * Get ChipIO audio stream's status. + */ +static void chipio_get_stream_control(struct hda_codec *codec, + int streamid, unsigned int *enable) +{ + chipio_set_control_param_no_mutex(codec, + CONTROL_PARAM_STREAM_ID, streamid); + *enable =3D snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, + VENDOR_CHIPIO_PARAM_GET, + CONTROL_PARAM_STREAM_CONTROL); +} =20 /* * Set sampling rate of the connection point. NO MUTEX. @@ -7513,6 +7525,109 @@ static void ca0132_refresh_widget_caps(struct hda_c= odec *codec) } } =20 + +/* If there is an active channel for some reason, find it and free it. */ +static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec) +{ + unsigned int i, tmp; + int status; + + /* Read active DSPDMAC channel register. */ + status =3D chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp); + if (status >=3D 0) { + /* AND against 0xfff to get the active channel bits. */ + tmp =3D tmp & 0xfff; + + /* If there are no active channels, nothing to free. */ + if (!tmp) + return; + } else { + codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n", + __func__); + return; + } + + /* + * Check each DSP DMA channel for activity, and if the channel is + * active, free it. + */ + for (i =3D 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) { + if (dsp_is_dma_active(codec, i)) { + status =3D dspio_free_dma_chan(codec, i); + if (status < 0) + codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n", + __func__, i); + } + } +} + +/* + * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in + * use, audio is no longer routed directly to the DAC/ADC from the HDA str= eam. + * Instead, audio is now routed through the DSP's DMA controllers, which + * the DSP is tasked with setting up itself. Through debugging, it seems t= he + * cause of most of the no-audio on startup issues were due to improperly + * configured DSP DMA channels. + * + * Normally, the DSP configures these the first time an HDA audio stream is + * started post DSP firmware download. That is why creating a 'dummy' stre= am + * worked in fixing the audio in some cases. This works most of the time, = but + * sometimes if a stream is started/stopped before the DSP can setup the D= MA + * configuration registers, it ends up in a broken state. Issues can also + * arise if streams are started in an unusual order, i.e the audio output = dma + * channel being sandwiched between the mic1 and mic2 dma channels. + * + * The solution to this is to make sure that the DSP has no DMA channels + * in use post DSP firmware download, and then to manually start each defa= ult + * DSP stream that uses the DMA channels. These are 0x0c, the audio output + * stream, 0x03, analog mic 1, and 0x04, analog mic 2. + */ +static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec) +{ + const unsigned int dsp_dma_stream_ids[] =3D { 0x0c, 0x03, 0x04 }; + struct ca0132_spec *spec =3D codec->spec; + unsigned int i, tmp; + + /* + * Check if any of the default streams are active, and if they are, + * stop them. + */ + mutex_lock(&spec->chipio_mutex); + + for (i =3D 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { + chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp); + + if (tmp) { + chipio_set_stream_control(codec, + dsp_dma_stream_ids[i], 0); + } + } + + mutex_unlock(&spec->chipio_mutex); + + /* + * If all DSP streams are inactive, there should be no active DSP DMA + * channels. Check and make sure this is the case, and if it isn't, + * free any active channels. + */ + ca0132_alt_free_active_dma_channels(codec); + + mutex_lock(&spec->chipio_mutex); + + /* Make sure stream 0x0c is six channels. */ + chipio_set_stream_channels(codec, 0x0c, 6); + + for (i =3D 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { + chipio_set_stream_control(codec, + dsp_dma_stream_ids[i], 1); + + /* Give the DSP some time to setup the DMA channel. */ + msleep(75); + } + + mutex_unlock(&spec->chipio_mutex); +} + /* * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio * router', where each entry represents a 48khz audio channel, with a form= at @@ -8250,6 +8365,7 @@ static void r3d_setup_defaults(struct hda_codec *code= c) =20 ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); + ca0132_alt_start_dsp_audio_streams(codec); =20 /*remove DSP headroom*/ tmp =3D FLOAT_ZERO; @@ -8300,6 +8416,7 @@ static void sbz_setup_defaults(struct hda_codec *code= c) =20 ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); + ca0132_alt_start_dsp_audio_streams(codec); sbz_connect_streams(codec); sbz_chipio_startup_data(codec); =20 @@ -8359,6 +8476,7 @@ static void ae5_setup_defaults(struct hda_codec *code= c) =20 ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); + ca0132_alt_start_dsp_audio_streams(codec); chipio_set_stream_control(codec, 0x03, 1); chipio_set_stream_control(codec, 0x04, 1); =20 @@ -8428,6 +8546,7 @@ static void ae7_setup_defaults(struct hda_codec *code= c) =20 ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); + ca0132_alt_start_dsp_audio_streams(codec); ae7_post_dsp_setup_ports(codec); =20 tmp =3D FLOAT_ZERO; --=20 2.25.1 From nobody Sat May 10 02:10:35 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607618224; cv=none; d=zohomail.com; s=zohoarc; b=La2hDef4ICFwmL8lfVQUrb8ZjObLcPYkDedYH0aRZrAD490/Qr2DGnpWnYAKROnM0vzGKg3sCuS7dWdBByNWKtEsl6YZPB0pallSgBAZf3+dmKsmqXr76leTXgCFzfjayX8jTyrTwNgqNTHp7/sogOEdN97YM1udQwy4OdQ0DH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607618224; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=sKdNFHIaOGHzemSXJ4fYnvyA7QI5pQyJsgsZg/WlZU8=; b=ckyp6G/yj8bDKi9J/wV1lUJ3iWciVgwo1tW4K/fu+NsJDmxLQ58JQa32By6GqokPpPVrtm+N6JpxykYPXOUuhd3dBbUp09kzv5lQDzTiuS++XBwuJkaHqdp1AiZkfBL97CKdkWZ5A1+Zaw31SCvaSNZqmSB08yXcTnI1fXF2rSw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1607618223989754.4643132306381; Thu, 10 Dec 2020 08:37:03 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392322AbgLJQK4 (ORCPT ); Thu, 10 Dec 2020 11:10:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392335AbgLJQHu (ORCPT ); Thu, 10 Dec 2020 11:07:50 -0500 Received: from mail-qt1-x830.google.com (mail-qt1-x830.google.com [IPv6:2607:f8b0:4864:20::830]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00EACC061794 for ; Thu, 10 Dec 2020 08:07:35 -0800 (PST) Received: by mail-qt1-x830.google.com with SMTP id j26so3885702qtq.8 for ; Thu, 10 Dec 2020 08:07:34 -0800 (PST) Received: from localhost.localdomain (cpe-71-65-111-223.cinci.res.rr.com. [71.65.111.223]) by smtp.googlemail.com with ESMTPSA id d190sm3852290qkf.112.2020.12.10.08.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 08:07:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sKdNFHIaOGHzemSXJ4fYnvyA7QI5pQyJsgsZg/WlZU8=; b=kPhh1k9RGQVw2nO38xkVOkwR/De1KOKnP+eCLe74yxRR6yA8+dGeGdUv/5lHWit/xq hc4MYYTiy25Jg9nprHcusjK6o+Ry13V6VxmHRC3LWNSy0nk/4Oa6Z+59spbrzxuCjz0G QitlL/rJwBRDdzhwYiOvEKmAyLIfYob+sXa0LqUOpu9h+jkjimy31b+Bx8DCnAbXNDSu UHSaA1ZVdDnaOgdhHjT88GakQegAhfpGxHqJjbKLOWu5WzLyQt5g4Nvm2IB9Yd1F4mey lGjULS4YXMISpc9p4wWffV3BtmOj9HpGJQ+WY2GgUr3rk596ZonYKW0uo0fLx3xPWMQA lnrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sKdNFHIaOGHzemSXJ4fYnvyA7QI5pQyJsgsZg/WlZU8=; b=llfQZLY/iTY8jps4BLAEFv2T9GaLSpm33W/b574tXrfbiRxWS/rwazsECZe8Hy2Exh 5w+kdpzKTcwTVHyKW3O6RwsX7MM1+XNJPpbl0dy5u2LY/Wk7Xvq32DF/00hKArisTBZX yMWWGGFeMEK9ZPx/JAkKSdhwa4OCXygYOexVZyNktJJ2Py1ysd3dsRmUZKbPB0mIJ7xk mhNefwgKS224NTbA1l/+fRHWRxa0bOo2/lwBAtT3G6GywT0QZ0w5HXR2iZLZWhRcyNTd C1IuIml9b1ejGiH8cXp3VhEi7whzCQN1Q0bRA99kJT02/NLcOn8ctD4s4ghak7MpShM5 ly7A== X-Gm-Message-State: AOAM5317gM7B81foIIcagi8+sB5tYbA1eHczbWjW2cbuYebqEbSNBRNc 4ObTZ4Jpc27a+mL5Q1iKGqI= X-Google-Smtp-Source: ABdhPJyD5Sr0PTnzWNkhnU3yKvolIcUB/EkRkxa//Z39Ut5HYtd2yLd8sNecVMYs8eXqtrZW/j27rA== X-Received: by 2002:aed:3051:: with SMTP id 75mr9959479qte.64.1607616454186; Thu, 10 Dec 2020 08:07:34 -0800 (PST) From: Connor McAdams Cc: conmanx360@gmail.com, Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] ALSA: hda/ca0132 - Remove now unnecessary DSP setup functions. Date: Thu, 10 Dec 2020 11:06:57 -0500 Message-Id: <20201210160658.461739-6-conmanx360@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201210160658.461739-1-conmanx360@gmail.com> References: <20201210160658.461739-1-conmanx360@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Now that the DSP's audio configuration is understood, remove previous hacky methods of trying to properly configure it. Signed-off-by: Connor McAdams --- sound/pci/hda/patch_ca0132.c | 105 ----------------------------------- 1 file changed, 105 deletions(-) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 8884ad0910cd..df8bee4eef26 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -2426,13 +2426,6 @@ static int dspio_set_uint_param(struct hda_codec *co= dec, int mod_id, sizeof(unsigned int)); } =20 -static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod= _id, - int req, const unsigned int data) -{ - return dspio_set_param(codec, mod_id, 0x00, req, &data, - sizeof(unsigned int)); -} - /* * Allocate a DSP DMA channel via an SCP message */ @@ -7780,24 +7773,6 @@ static void ca0132_alt_init_speaker_tuning(struct hd= a_codec *codec) SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); } =20 -/* - * Creates a dummy stream to bind the output to. This seems to have to be = done - * after changing the main outputs source and destination streams. - */ -static void ca0132_alt_create_dummy_stream(struct hda_codec *codec) -{ - struct ca0132_spec *spec =3D codec->spec; - unsigned int stream_format; - - stream_format =3D snd_hdac_calc_stream_format(48000, 2, - SNDRV_PCM_FORMAT_S32_LE, 32, 0); - - snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, - 0, stream_format); - - snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); -} - /* * Initialize mic for non-chromebook ca0132 implementations. */ @@ -7839,9 +7814,6 @@ static void sbz_connect_streams(struct hda_codec *cod= ec) =20 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); =20 - chipio_set_stream_channels(codec, 0x0C, 6); - chipio_set_stream_control(codec, 0x0C, 1); - /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ chipio_write_no_mutex(codec, 0x18a020, 0x00000043); =20 @@ -7889,9 +7861,6 @@ static void sbz_chipio_startup_data(struct hda_codec = *codec) break; } =20 - chipio_set_stream_channels(codec, 0x0c, 6); - chipio_set_stream_control(codec, 0x0c, 1); - if (dsp_out_remap_data) chipio_remap_stream(codec, dsp_out_remap_data); =20 @@ -7899,57 +7868,6 @@ static void sbz_chipio_startup_data(struct hda_codec= *codec) mutex_unlock(&spec->chipio_mutex); } =20 -/* - * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. Th= is is - * done after the DSP is loaded. - */ -static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec) -{ - struct ca0132_spec *spec =3D codec->spec; - unsigned int tmp, i; - - /* - * Gotta run these twice, or else mic works inconsistently. Not clear - * why this is, but multiple tests have confirmed it. - */ - for (i =3D 0; i < 2; i++) { - switch (ca0132_quirk(spec)) { - case QUIRK_SBZ: - case QUIRK_AE5: - case QUIRK_AE7: - tmp =3D 0x00000003; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - tmp =3D 0x00000000; - dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); - tmp =3D 0x00000001; - dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); - tmp =3D 0x00000004; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - tmp =3D 0x00000005; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - tmp =3D 0x00000000; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - break; - case QUIRK_R3D: - case QUIRK_R3DI: - tmp =3D 0x00000000; - dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); - tmp =3D 0x00000001; - dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); - tmp =3D 0x00000004; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - tmp =3D 0x00000005; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - tmp =3D 0x00000000; - dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); - break; - default: - break; - } - msleep(100); - } -} - static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) { struct ca0132_spec *spec =3D codec->spec; @@ -8067,9 +7985,6 @@ static void ae5_post_dsp_stream_setup(struct hda_code= c *codec) =20 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); =20 - chipio_set_stream_channels(codec, 0x0C, 6); - chipio_set_stream_control(codec, 0x0C, 1); - chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); =20 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); @@ -8127,9 +8042,6 @@ static void ae7_post_dsp_setup_ports(struct hda_codec= *codec) =20 mutex_lock(&spec->chipio_mutex); =20 - chipio_set_stream_channels(codec, 0x0c, 6); - chipio_set_stream_control(codec, 0x0c, 1); - /* Seems to share the same port remapping as the SBZ. */ chipio_remap_stream(codec, &stream_remap_data[1]); =20 @@ -8155,8 +8067,6 @@ static void ae7_post_dsp_asi_stream_setup(struct hda_= codec *codec) ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); =20 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); - chipio_set_stream_channels(codec, 0x0c, 6); - chipio_set_stream_control(codec, 0x0c, 1); =20 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); @@ -8363,7 +8273,6 @@ static void r3d_setup_defaults(struct hda_codec *code= c) if (spec->dsp_state !=3D DSP_DOWNLOADED) return; =20 - ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); =20 @@ -8414,15 +8323,11 @@ static void sbz_setup_defaults(struct hda_codec *co= dec) if (spec->dsp_state !=3D DSP_DOWNLOADED) return; =20 - ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); sbz_connect_streams(codec); sbz_chipio_startup_data(codec); =20 - chipio_set_stream_control(codec, 0x03, 1); - chipio_set_stream_control(codec, 0x04, 1); - /* * Sets internal input loopback to off, used to have a switch to * enable input loopback, but turned out to be way too buggy. @@ -8457,8 +8362,6 @@ static void sbz_setup_defaults(struct hda_codec *code= c) } =20 ca0132_alt_init_speaker_tuning(codec); - - ca0132_alt_create_dummy_stream(codec); } =20 /* @@ -8474,11 +8377,8 @@ static void ae5_setup_defaults(struct hda_codec *cod= ec) if (spec->dsp_state !=3D DSP_DOWNLOADED) return; =20 - ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); - chipio_set_stream_control(codec, 0x03, 1); - chipio_set_stream_control(codec, 0x04, 1); =20 /* New, unknown SCP req's */ tmp =3D FLOAT_ZERO; @@ -8527,8 +8427,6 @@ static void ae5_setup_defaults(struct hda_codec *code= c) } =20 ca0132_alt_init_speaker_tuning(codec); - - ca0132_alt_create_dummy_stream(codec); } =20 /* @@ -8544,7 +8442,6 @@ static void ae7_setup_defaults(struct hda_codec *code= c) if (spec->dsp_state !=3D DSP_DOWNLOADED) return; =20 - ca0132_alt_dsp_scp_startup(codec); ca0132_alt_init_analog_mics(codec); ca0132_alt_start_dsp_audio_streams(codec); ae7_post_dsp_setup_ports(codec); @@ -8613,8 +8510,6 @@ static void ae7_setup_defaults(struct hda_codec *code= c) } =20 ca0132_alt_init_speaker_tuning(codec); - - ca0132_alt_create_dummy_stream(codec); } =20 /* --=20 2.25.1