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[2a01:cb00:8bd:2700:d88:c772:3353:ad1a]) by smtp.gmail.com with ESMTPSA id w21sm3743843wmi.45.2021.01.13.09.38.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 09:38:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gEkFSZe9SIX9zzKDioat+7g6Vgf10UlxyWUaHkxXgCY=; b=P2Elyu8cZkWvOF7/Y4x7dchJd2tgnm9LGWHUKAn/nWFEYoYCQdYW9hJy2Soop9BZPX WARIbOpx4O0Wk38wjkAYLKRmNUyuZfJIeVvbL1UxViAHiALzayrazauirsPmnVjn02/R fm1LVeiwuhHYYZSUJWO81VtiQ7HgjziO0SVEFePCU6+KmpcHobYpggSg7mR9Oc2I9XhD XESfmNSnK6KTraFpM0KOAjb70EHeKlMlV4G32gvYDe+wKehz/k7aOEyWa0oPihigu7GJ eEAvIS1Yl0c/BNH0fX2ANG2RMsOWzG+soSBrr6me+kd+IAMuLo5ZiyORU3QzwsKMYqHC hZIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gEkFSZe9SIX9zzKDioat+7g6Vgf10UlxyWUaHkxXgCY=; b=mBzyrLw+vGTpmzUK95VCcbPKdJjON6ZlifCa9Q0Ni1jIjr8o8DUzl6OXrkBdc9XDnO 370HpSU40H3p+bF0LAZzKOnFVEoDJn7LuDafg1K29dFZJdugt4Oef8kkm5V8v7HtiBwu Flg92UM6TZ3gyI+omJamAXBj+sQp9oKcc7XiUK3imIA/Wbw40wGlSgRjbyzzb99oKwxs 4gkkT+qasityZAnUMr5I+FHgUX64UAlA7gtkag+Wi64Q6epfWpmPc9Xj1jisAzty1vLX xn1AUxe8JL/dGBnw6hOTb7IYfYmeWBgZLnPq+moNutdmY3RQNhAC4TdpYHsIQL/rXuzI eo3Q== X-Gm-Message-State: AOAM532j3gdsG1xyH1QN+Dj29zlK/tFjBnuhZT4qdbDVU4dVJr/TffaO RGOGwsg4iRhr6dIOjghRG0Q= X-Google-Smtp-Source: ABdhPJwrSy1GhyKJTTPpxBUa8PWLt5rY7VLDaiEXlYjz+NmsRNlNWYRvUCD4OwxnIvWomB97cb1Jiw== X-Received: by 2002:a5d:4d50:: with SMTP id a16mr3652101wru.43.1610559539460; Wed, 13 Jan 2021 09:38:59 -0800 (PST) From: Adrien Grassein Cc: krzk@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Adrien Grassein Subject: [PATCH v3 2/3] arm64: dts: imx: Add i.mx8mm nitrogen8mm basic dts support Date: Wed, 13 Jan 2021 18:38:54 +0100 Message-Id: <20210113173855.1509417-3-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210113173855.1509417-1-adrien.grassein@gmail.com> References: <20210113173855.1509417-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Tested with a basic Build Root configuration booting from sdcard. Signed-off-by: Adrien Grassein --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-nitrogen8mm_rev2.dts | 417 ++++++++++++++++++ 2 files changed, 418 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-nitrogen8mm_rev2.d= ts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 901d80086b47..b2eb7a5e4db3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-librem5-devkit.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-librem5-r2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-librem5-r3.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-nitrogen.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-nitrogen8mm_rev2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-phanbell.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-pico-pi.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-thor96.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen8mm_rev2.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-nitrogen8mm_rev2.dts new file mode 100644 index 000000000000..a83fa8d05e81 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen8mm_rev2.dts @@ -0,0 +1,417 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Boundary Devices i.MX8MMini Nitrogen8MM Rev2 board. + * Adrien Grassein + */ +/dts-v1/; +#include "imx8mm.dtsi" + +/ { + model =3D "Boundary Devices i.MX8MMini Nitrogen8MM Rev2"; + compatible =3D "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm"; +}; + +&A53_0 { + cpu-supply =3D <®_sw3>; +}; + +&A53_1 { + cpu-supply =3D <®_sw3>; +}; + +&A53_2 { + cpu-supply =3D <®_sw3>; +}; + +&A53_3 { + cpu-supply =3D <®_sw3>; +}; + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec1>; + + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + ethphy0: ethernet-phy@4 { + compatible =3D "ethernet-phy-id004d.d072", + "ethernet-phy-ieee802.3-c22"; + reg =3D <4>; + interrupts-extended =3D <&gpio3 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c1>; + pinctrl-1 =3D <&pinctrl_i2c1_1>; + scl-gpios =3D <&gpio5 14 GPIO_OPEN_DRAIN>; + sda-gpios =3D <&gpio5 15 GPIO_OPEN_DRAIN>; + status =3D "okay"; + + pmic@8 { + compatible =3D "nxp,pf8121a"; + reg =3D <0x8>; + status =3D "okay"; + + regulators { + reg_ldo1: ldo1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <1500000>; + }; + + reg_ldo2: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <1500000>; + }; + + reg_ldo3: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <1500000>; + }; + + reg_ldo4: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <1500000>; + }; + + reg_buck1: buck1 { + nxp,ilim-ma =3D <4500>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <400000>; + }; + + reg_buck2: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <400000>; + }; + + reg_sw3: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <400000>; + }; + + reg_buck4: buck4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <400000>; + }; + + reg_buck5: buck5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <400000>; + }; + + reg_buck6: buck6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <400000>; + }; + + reg_buck7: buck7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + }; + + reg_vsnvs: vsnvs { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <1800000>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c3>; + pinctrl-1 =3D <&pinctrl_i2c3_1>; + scl-gpios =3D <&gpio5 18 GPIO_OPEN_DRAIN>; + sda-gpios =3D <&gpio5 19 GPIO_OPEN_DRAIN>; + status =3D "okay"; + + i2cmux@70 { + compatible =3D "nxp,pca9540"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c3@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + rtc@68 { + compatible =3D "microcrystal,rv4162"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3a_rv4162>; + reg =3D <0x68>; + interrupts-extended =3D <&gpio4 22 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; + }; + }; +}; + +/* console */ +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + assigned-clocks =3D <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents =3D <&clk IMX8MM_CLK_24M>; + status =3D "okay"; +}; + +/* eMMC */ +&usdhc1 { + bus-width =3D <8>; + sdhci-caps-mask =3D <0x80000000 0x0>; + non-removable; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + status =3D "okay"; +}; + +/* sdcard */ +&usdhc2 { + bus-width =3D <4>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>; + status =3D "okay"; + vqmmc-supply =3D <®_ldo2>; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog>; + + pinctrl_fec1: fec1grp { + fsl,pins =3D < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x159 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x09 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x09 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_1: i2c1-1grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3_1: i2c3-1grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + + pinctrl_i2c3a_rv4162: i2c3a-rv4162grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x141 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140 + >; + }; + +}; --=20 2.25.1