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[2a01:cb00:8bd:2700:9031:1bc0:a820:c7e4]) by smtp.gmail.com with ESMTPSA id l7sm13414853wme.4.2021.01.15.13.01.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 13:01:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WfibYL5xNahX8LA5CAFj5sU2ovXxAFSThLjIDqOxaPY=; b=rA60KlIhKOzTBmP86uDmhv8WygC91158Qmb51GkclM0oatiLUs1RJJhVifO7hvNMrq LM864x76r9DdHOy05IsedYZdAIYtTKPey6w3XOgFA5hDE+F43NtFyZKdbXvXvFs+ZNcR Af817Ck6vEDNdaXp/p29ApHUcvrw7LrMAQsFA4OBjxaXKeCD6ibtk6BaQutq3uhovpWB uaWjMgfNPbUZqOS++MUvgWVAiQNi3G5rneghX5dlcvy7o+HEH+yCCQ4sHTblF5jbLagj 3+GA6s3Ggb50sUkS3UhIOz5ZBeR6qNua1SMsOd0VgHkkZcmkrrs1TEgzRPpIvGTKRdg6 XqAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WfibYL5xNahX8LA5CAFj5sU2ovXxAFSThLjIDqOxaPY=; b=Pj1hyoDhT2nnNjGzuzDacFIQ6Tz/62d62YyMcSaltKupJn5NfA4Hc/NB/ndLqNg2ah 1Vkmr8lgqBSmUKjrR1iwcoTBzRuEXZ/RYdCOF3slwlbir5YQM/ze5C/tErmczTNnpDuI x3MjYdm2BNCZ63pBZjw7PIqgVR1V68VeTnra+m8039ie7TnTE4bh00XzYn+sEoR8ff/H RX3V/sPmb2kLiH2+LPsBJpcI14LqBzRUIQxgsmdnOS9MzC7LrEnhE9LHbKg8UwOi0o1v C3ZbdYq39ryOwxaN1rVfXgBGBcuYNucQrb+hrrl1xcJrpSo48RBS0sqh3qx1X60cxsyh 1aEQ== X-Gm-Message-State: AOAM533BlLQ10ErTzUc9A0asC21WOuHTrPppelWBasJB6QD9CY96KL24 ejB6Eouy09UbdTCAvy2klec= X-Google-Smtp-Source: ABdhPJztA5WpQlPCB0XMVSoCocG3bBFQ5htNLRg8cH0zK1pfUyg0Ow/xSc+c7X6xNMLrtYoUShBzdw== X-Received: by 2002:a5d:5917:: with SMTP id v23mr15481989wrd.308.1610744488194; Fri, 15 Jan 2021 13:01:28 -0800 (PST) From: Adrien Grassein Cc: krzk@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Adrien Grassein Subject: [PATCH v4 1/3] dt-bindings: arm: imx: add imx8mm nitrogen support Date: Fri, 15 Jan 2021 22:01:22 +0100 Message-Id: <20210115210124.507282-2-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115210124.507282-1-adrien.grassein@gmail.com> References: <20210115210124.507282-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The Nitrogen8M Mini is an ARM based single board computer (SBC). Signed-off-by: Adrien Grassein Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 2ae66407e2aa..30e126c421f2 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -674,6 +674,7 @@ properties: items: - enum: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit + - boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development = Kit --=20 2.25.1 From nobody Sat May 10 03:46:32 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610744572; cv=none; d=zohomail.com; s=zohoarc; b=hpukjZ4BSXjjl7Ou7vm0RRWw3YwiJCpzftbJf0ps3Ie12SZ9cJLJkhhc8RKI/KIOWJex28sssIUT2gxy4b3oKjBVuF0e9OwPZkJzcKi61JZPLQWcY6gJ4Ic6WbPG2n8hSTqlAzrhcRakVz6qlZlYypk5U7HBy1lEtycW7MeDFw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610744572; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=AT+P7GUlYg4ERL6NwcEjeODLsxvSXvrDXLKs1As1S4k=; b=DBwxqpEypKJjLDPBhsM3Y2cBWK9KyVrqlHY472OyyBzWzbaA/L07N3hGG24CTN7blESuZtj5O8ui65CHuf/xRwKOqiRdvXvqjiDoM5rBRQkrOkmPJBv/hZzKnKM/L66Rz6LU23v/Z9RDr4GqhKxKYIGIYE6GBoPw7PVc/nmTT80= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1610744572891943.9057785972965; Fri, 15 Jan 2021 13:02:52 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388744AbhAOVC0 (ORCPT ); Fri, 15 Jan 2021 16:02:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388661AbhAOVCU (ORCPT ); Fri, 15 Jan 2021 16:02:20 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 672F4C06179C; Fri, 15 Jan 2021 13:01:30 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id u14so4544759wmq.4; Fri, 15 Jan 2021 13:01:30 -0800 (PST) Received: from localhost.localdomain (2a01cb0008bd270090311bc0a820c7e4.ipv6.abo.wanadoo.fr. [2a01:cb00:8bd:2700:9031:1bc0:a820:c7e4]) by smtp.gmail.com with ESMTPSA id l7sm13414853wme.4.2021.01.15.13.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 13:01:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AT+P7GUlYg4ERL6NwcEjeODLsxvSXvrDXLKs1As1S4k=; b=gkVGDWgHONCwIMgrS7GVcd8jd03nJGyfaRdaidtLgF0DoS2hf/6gmAY7+5zLfTN8kv 5EIlgD3zf2YVWWB2TddXdQFRbiiTcxxH8qqWYkhefxTFcVe9QKuN3fVwkat44mVqvYIz 5EhOH92SiQvQLQo1iKQR8ApccjiyBvu5dr9d6FJkHddsAlvquZWHQqZnqU6Pfrcrzqgq 6tA687QHwuE+qsEQx0ZO70nigFS8px56uLGzc6OsAmwGqiscj8lEfCU0803J57b15bq2 VfmeDO46uKPk27CnwYl4LkBRSlZ0BQNA1Rl8+0IDwAQ6gjckKp6Ol4xLBfMSMp0kH7rf 0Gww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AT+P7GUlYg4ERL6NwcEjeODLsxvSXvrDXLKs1As1S4k=; b=Ml+9UQJ6q8xGUoRbNbtieGPSlmEwkIvaf4PTM6FAbBpbRCrRPIzolgvvsWJdzjRjcC oc6OCpwHU30iTbinHhSQQyVqtOrXjxAr0pmHy7jyJ5VVhDg/P7Hsz2sALswq+E151jQp a5Jnz83b5BJiuqfgZj/xoIot7/XjAWQgIlDKIDxVnPVi/ZmyEf6rprBSej+Tfv8iUinR 81685/nqhtKoVmRgruyelHkejVHTZcZPiNQynkZFKLDEhULfp4v3GQNSb8U/z9zdZRLN Ia85oMorqscHkehr2Hpr/pJjBpcSUf1Uli69odq4obuUkfhYlgNI9WXgVfk7aHOFBAV4 hWVg== X-Gm-Message-State: AOAM531tkZxIwPVRoNe05w5AzFAu55lrdL7CIBDdjRh2XEvLGyUauu32 cBpPSdUo4dfh5gFyHsvSbGc= X-Google-Smtp-Source: ABdhPJysuGCXww6h4+rEeHxwLvZOPGzlXGb5WesIkZ+Tp7oxiEzTT5N54CiNCeXUu4UiHcNbMKcspA== X-Received: by 2002:a7b:cb9a:: with SMTP id m26mr10379606wmi.130.1610744489132; Fri, 15 Jan 2021 13:01:29 -0800 (PST) From: Adrien Grassein Cc: krzk@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Adrien Grassein Subject: [PATCH v4 2/3] arm64: dts: imx: Add i.mx8mm nitrogen8mm basic dts support Date: Fri, 15 Jan 2021 22:01:23 +0100 Message-Id: <20210115210124.507282-3-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115210124.507282-1-adrien.grassein@gmail.com> References: <20210115210124.507282-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Tested with a basic Build Root configuration booting from sdcard. Signed-off-by: Adrien Grassein --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-nitrogen8mm_rev2.dts | 415 ++++++++++++++++++ 2 files changed, 416 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-nitrogen8mm_rev2.d= ts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 38559943c15d..398b5cb4f3e2 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-librem5-devkit.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-librem5-r2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-librem5-r3.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-nitrogen.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-nitrogen8mm_rev2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-phanbell.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-pico-pi.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-thor96.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen8mm_rev2.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-nitrogen8mm_rev2.dts new file mode 100644 index 000000000000..e89fbf512f9e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen8mm_rev2.dts @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Boundary Devices i.MX8MMini Nitrogen8MM Rev2 board. + * Adrien Grassein + */ +/dts-v1/; +#include "imx8mm.dtsi" + +/ { + model =3D "Boundary Devices i.MX8MMini Nitrogen8MM Rev2"; + compatible =3D "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm"; +}; + +&A53_0 { + cpu-supply =3D <®_sw3>; +}; + +&A53_1 { + cpu-supply =3D <®_sw3>; +}; + +&A53_2 { + cpu-supply =3D <®_sw3>; +}; + +&A53_3 { + cpu-supply =3D <®_sw3>; +}; + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec1>; + + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + ethphy0: ethernet-phy@4 { + compatible =3D "ethernet-phy-id004d.d072", + "ethernet-phy-ieee802.3-c22"; + reg =3D <4>; + interrupts-extended =3D <&gpio3 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c1>; + pinctrl-1 =3D <&pinctrl_i2c1_1>; + scl-gpios =3D <&gpio5 14 GPIO_OPEN_DRAIN>; + sda-gpios =3D <&gpio5 15 GPIO_OPEN_DRAIN>; + status =3D "okay"; + + pmic@8 { + compatible =3D "nxp,pf8121a"; + reg =3D <0x8>; + status =3D "okay"; + + regulators { + reg_ldo1: ldo1 { + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_ldo2: ldo2 { + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_ldo3: ldo3 { + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_ldo4: ldo4 { + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck1: buck1 { + regulator-min-microvolt =3D <400000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck2: buck2 { + regulator-min-microvolt =3D <400000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_sw3: buck3 { + regulator-min-microvolt =3D <400000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck4: buck4 { + regulator-min-microvolt =3D <400000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck5: buck5 { + regulator-min-microvolt =3D <400000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck6: buck6 { + regulator-min-microvolt =3D <400000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck7: buck7 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vsnvs: vsnvs { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c3>; + pinctrl-1 =3D <&pinctrl_i2c3_1>; + scl-gpios =3D <&gpio5 18 GPIO_OPEN_DRAIN>; + sda-gpios =3D <&gpio5 19 GPIO_OPEN_DRAIN>; + status =3D "okay"; + + i2cmux@70 { + compatible =3D "nxp,pca9540"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c3@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + rtc@68 { + compatible =3D "microcrystal,rv4162"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3a_rv4162>; + reg =3D <0x68>; + interrupts-extended =3D <&gpio4 22 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; + }; + }; +}; + +/* console */ +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + assigned-clocks =3D <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents =3D <&clk IMX8MM_CLK_24M>; + status =3D "okay"; +}; + +/* eMMC */ +&usdhc1 { + bus-width =3D <8>; + sdhci-caps-mask =3D <0x80000000 0x0>; + non-removable; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + status =3D "okay"; +}; + +/* sdcard */ +&usdhc2 { + bus-width =3D <4>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>; + status =3D "okay"; + vqmmc-supply =3D <®_ldo2>; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog>; + + pinctrl_fec1: fec1grp { + fsl,pins =3D < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x159 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x09 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x09 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_1: i2c1-1grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3_1: i2c3-1grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + + pinctrl_i2c3a_rv4162: i2c3a-rv4162grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x141 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140 + >; + }; +}; --=20 2.25.1 From nobody Sat May 10 03:46:32 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610744571; cv=none; d=zohomail.com; s=zohoarc; b=SHgoIRIHDO5FTwJ0msOmJ3OLz9+FP5QTx0pf5WYNFGBkM74KouRha0bTT3mQ/kqlEiFcWH+/bvdf+9laCRcHLrH6AcrpYMM6WLzGICCCy8tOrRTlNPZZjxz63v18BZN9CtNR/hEQSgMeCbveM3WpSlYCPOyH5clp8k3fD6IsuQc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610744571; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; 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[2a01:cb00:8bd:2700:9031:1bc0:a820:c7e4]) by smtp.gmail.com with ESMTPSA id l7sm13414853wme.4.2021.01.15.13.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 13:01:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LEzohCRsK+Jzaxz+SANVOLWTAoH1HEg4LQDGbyq7c0o=; b=VD+rTQiNM6uXyQBYmwDXV81j7ywhaUNtBqPfiq4Op2JgxB+14ghSpxI0EViBf7rHVs LVNVhhlFOZWfVAnIptmVJbM7DuC2G9q4tUdYQmWo2++y+7rUdKfBwK1o/Dih9ObssR3k uEE81VtxzZ0M429oyptd/ZIWWb072RzKUIPkPu9UBcsvpa5aYPRwg4yBtgnYKawd/LyM ErgqFRP9PWnuWIiGHisCucF/WmW/BxqobQRvcf9zwZSHbXhoinOpgzRi6uZFd+wXTRNk 50hzFPC0ily05UUGxu/UlXhaoxNWa4xRnUKSIxNUGFokVkVBQqc9ebyrIgUV0165RegF MJpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LEzohCRsK+Jzaxz+SANVOLWTAoH1HEg4LQDGbyq7c0o=; b=rWyVbPYBkjt6Oe8u+ztaSKibEOaRb0EN6TJgEeaZvDwR7hchwRSbFY4z/TgVOWVbcD xVHwfBKDRQb5XI3sNGYVd8xIy8dVArMzLzo9AgjcLkQe52kJ2Qx/WYhQPgzmNPJXOnxi Fd4cgCpPS0OevwA+RocsDZvIWcaq7wHm/5UPbsQthVrrMerPvTryfbBS+0yLm3W6iEm2 rJXtKXzvqerxhLzDWst8PUzcWj7Anm97LZFQX/AAzhvM7LRgv29ikejBnd4srgjukSHi dsSxSITnrUPfpKTYAksTmAHR9caF4XQsT+3hey69LiWr3oPJxhaXL+BJIi71oL1WV/zV 3p0w== X-Gm-Message-State: AOAM530Kpz9eWGDHf0SK0cGSguDVFKHLv4hBJRHsZ0r9y9bHMkLu5x0e CcdhDMBuZr3MiBNLK6pGTHY= X-Google-Smtp-Source: ABdhPJzYao0HWnOejl6JP2t3R52ey+WuKckBJelKydLHQMjZyHCZNwYZUPLNN4fOW8w8O86NpX9RdQ== X-Received: by 2002:a5d:4a09:: with SMTP id m9mr15201327wrq.359.1610744489776; Fri, 15 Jan 2021 13:01:29 -0800 (PST) From: Adrien Grassein Cc: krzk@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Adrien Grassein Subject: [PATCH v4 3/3] arm64: defconfig: Enable PF8x00 as builtin Date: Fri, 15 Jan 2021 22:01:24 +0100 Message-Id: <20210115210124.507282-4-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115210124.507282-1-adrien.grassein@gmail.com> References: <20210115210124.507282-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This driver is mandatory for the nitrogen8m mini board when booting from the sdcard slot. Signed-off-by: Adrien Grassein --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 9957b6669eb1..de90f42419a3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -606,6 +606,7 @@ CONFIG_REGULATOR_MAX77620=3Dy CONFIG_REGULATOR_MAX8973=3Dy CONFIG_REGULATOR_MP8859=3Dy CONFIG_REGULATOR_PCA9450=3Dy +CONFIG_REGULATOR_PF8X00=3Dy CONFIG_REGULATOR_PFUZE100=3Dy CONFIG_REGULATOR_PWM=3Dy CONFIG_REGULATOR_QCOM_RPMH=3Dy --=20 2.25.1