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Wed, 27 Jan 2021 13:46:29 +0300 Received: by iva6-2d18925256a6.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id AUuDuROonk-kSm8U3AH; Wed, 27 Jan 2021 13:46:28 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1611744389; bh=MjRDgxGTiCbkvysV4oEPs6x8SIGM1B5dcgTPZ1aY3Hg=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=DxJtolUZBvHzxGkJokYKrlzSmVHC0e6oR0Re2a/Dp7m4FD/qX9HFZwlmRBj1BQTiH Lj9G39msGPaq4uIl4ecXJtZZOKLlAFRrN9M6qn9QLCLS2wHy6Bm2lQB4z2yXg3g1vr +HBnOHtekr+DcAEnuiHO5Y/f+9ow0TPCtoRHZ5eo= Authentication-Results: iva3-4874dd324817.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Bartosz Golaszewski , Alexander Sverdlin , Maulik Shah , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/9] gpio: ep93xx: Fix single irqchip with multi gpiochips Date: Wed, 27 Jan 2021 13:46:10 +0300 Message-Id: <20210127104617.1173-3-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210127104617.1173-1-nikita.shubin@maquefel.me> References: <20201228150052.2633-1-nikita.shubin@maquefel.me> <20210127104617.1173-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Fixes the following warnings which results in interrupts disabled on=20 port B/F: gpio gpiochip1: (B): detected irqchip that is shared with multiple gpiochip= s: please fix the driver. gpio gpiochip5: (F): detected irqchip that is shared with multiple gpiochip= s: please fix the driver. - added separate irqchip for each interrupt capable gpiochip - provided unique names for each irqchip - reworked ep93xx_gpio_port to make it usable before chip_add_data=20 in ep93xx_init_irq_chips Fixes: a8173820f441 ("gpio: gpiolib: Allow GPIO IRQs to lazy disable") Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 45 ++++++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 0d0435c07a5a..2eea02c906e0 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -34,9 +34,12 @@ */ #define EP93XX_GPIO_F_IRQ_BASE 80 =20 +#define EP93XX_GPIO_IRQ_CHIPS_NUM 3 + struct ep93xx_gpio { void __iomem *base; struct gpio_chip gc[8]; + struct irq_chip ic[EP93XX_GPIO_IRQ_CHIPS_NUM]; }; =20 /* @@ -55,6 +58,11 @@ static unsigned char gpio_int_type2[3]; static unsigned char gpio_int_debounce[3]; =20 /* Port ordering is: A B F */ +static const char * const irq_chip_names[] =3D { + "gpio-irq-a", + "gpio-irq-b", + "gpio-irq-f" +}; static const u8 int_type1_register_offset[3] =3D { 0x90, 0xac, 0x4c }; static const u8 int_type2_register_offset[3] =3D { 0x94, 0xb0, 0x50 }; static const u8 eoi_register_offset[3] =3D { 0x98, 0xb4, 0x54 }; @@ -77,9 +85,8 @@ static void ep93xx_gpio_update_int_params(struct ep93xx_g= pio *epg, unsigned port epg->base + int_en_register_offset[port]); } =20 -static int ep93xx_gpio_port(struct gpio_chip *gc) +static int ep93xx_gpio_port(struct ep93xx_gpio *epg, struct gpio_chip *gc) { - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); int port =3D 0; =20 while (port < ARRAY_SIZE(epg->gc) && gc !=3D &epg->gc[port]) @@ -101,7 +108,7 @@ static void ep93xx_gpio_int_debounce(struct gpio_chip *= gc, unsigned int offset, bool enable) { struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); + int port =3D ep93xx_gpio_port(epg, gc); int port_mask =3D BIT(offset); =20 if (enable) @@ -163,7 +170,7 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); + int port =3D ep93xx_gpio_port(epg, gc); int port_mask =3D BIT(d->irq & 7); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) { @@ -178,7 +185,7 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); + int port =3D ep93xx_gpio_port(epg, gc); int port_mask =3D BIT(d->irq & 7); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) @@ -194,7 +201,7 @@ static void ep93xx_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); + int port =3D ep93xx_gpio_port(epg, gc); =20 gpio_int_unmasked[port] &=3D ~BIT(d->irq & 7); ep93xx_gpio_update_int_params(epg, port); @@ -204,7 +211,7 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); + int port =3D ep93xx_gpio_port(epg, gc); =20 gpio_int_unmasked[port] |=3D BIT(d->irq & 7); ep93xx_gpio_update_int_params(epg, port); @@ -219,7 +226,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, uns= igned int type) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); + int port =3D ep93xx_gpio_port(epg, gc); int offset =3D d->irq & 7; int port_mask =3D BIT(offset); irq_flow_handler_t handler; @@ -335,6 +342,22 @@ static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, = unsigned offset) return EP93XX_GPIO_F_IRQ_BASE + offset; } =20 +static void ep93xx_init_irq_chips(struct ep93xx_gpio *epg) +{ + int i; + + for (i =3D 0; i < EP93XX_GPIO_IRQ_CHIPS_NUM; i++) { + struct irq_chip *ic =3D &epg->ic[i]; + + ic->name =3D irq_chip_names[i]; + ic->irq_ack =3D ep93xx_gpio_irq_ack; + ic->irq_mask_ack =3D ep93xx_gpio_irq_mask_ack; + ic->irq_mask =3D ep93xx_gpio_irq_mask; + ic->irq_unmask =3D ep93xx_gpio_irq_unmask; + ic->irq_set_type =3D ep93xx_gpio_irq_type; + } +} + static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct platform_device *pdev, struct ep93xx_gpio *epg, @@ -345,6 +368,7 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev =3D &pdev->dev; struct gpio_irq_chip *girq; int err; + int port; =20 err =3D bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0); if (err) @@ -356,7 +380,8 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, girq =3D &gc->irq; if (bank->has_irq || bank->has_hierarchical_irq) { gc->set_config =3D ep93xx_gpio_set_config; - girq->chip =3D &ep93xx_gpio_irq_chip; + port =3D ep93xx_gpio_port(epg, gc); + girq->chip =3D &epg->ic[port]; } =20 if (bank->has_irq) { @@ -423,6 +448,8 @@ static int ep93xx_gpio_probe(struct platform_device *pd= ev) if (IS_ERR(epg->base)) return PTR_ERR(epg->base); =20 + ep93xx_init_irq_chips(epg); + for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { struct gpio_chip *gc =3D &epg->gc[i]; struct ep93xx_gpio_bank *bank =3D &ep93xx_gpio_banks[i]; --=20 2.29.2