From nobody Mon Dec 15 01:52:03 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=quarantine dis=quarantine) header.from=ti.com ARC-Seal: i=1; a=rsa-sha256; t=1611847829; cv=none; d=zohomail.com; s=zohoarc; b=QUvMvBxxiRFfHCypfv54EBmOgvL4UduFUeKpbJCUFYqmr/OXrv1giZFphhs1KiFi3Fx7wDTHc7yJTigK7hhBqgEb9wVQAaRCwazMgaee250e9bnV5edTSkK1HygVgXaBuH1HpR6nf/GD0HCQKSBMOmSaaNMUuzgcvW+8Pk+dmHA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611847829; h=Content-Type:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=0x5nGBBd8lDolKR3x+YbTSeWqe7UCmB3rIQ1gpq8PKg=; b=B7nt9LJT1jC6vYpRlCS7OtO6fzpRCXN9/xAhMx37k6npsTJokbsSfL/wds777F5WMJc1OIfo9OYaJlubb6kSXpGdp8wA/RiMXgkjMl8Wd1szAGGgxCGG+Ft8DKiX8zEohHxv7l12xTF8ch6AUdZz9WhU76dlNLJlaln4rn7payI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=quarantine dis=quarantine) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1611847829139924.776715792072; Thu, 28 Jan 2021 07:30:29 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232306AbhA1P3v (ORCPT ); Thu, 28 Jan 2021 10:29:51 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:40804 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231663AbhA1P3e (ORCPT ); Thu, 28 Jan 2021 10:29:34 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 10SFRu07069381; Thu, 28 Jan 2021 09:27:56 -0600 Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 10SFRu8b017449 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 28 Jan 2021 09:27:56 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 28 Jan 2021 09:27:55 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 28 Jan 2021 09:27:55 -0600 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 10SFRk5B094536; Thu, 28 Jan 2021 09:27:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1611847676; bh=0x5nGBBd8lDolKR3x+YbTSeWqe7UCmB3rIQ1gpq8PKg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tLu8cXKtqGTB4sgoPyGC5YDtegUXsEdmadAjACfFkjOv7dHy0JP8k724kU0PIPTgB sQHEbqArzyixKAJzLWf0DCm5EAhM58ONoESbygwH0SiwUNbu8w/pLC7g+eXJ1xARko 57cTbTlt4iIJmMlT1xKKtF6S4lQI/ZAHBmmQQkVc= From: Aswath Govindraju CC: Lokesh Vutla , Vignesh Raghavendra , Kishon Vijay Abraham I , Sekhar Nori , Faiz Abbas , Aswath Govindraju , Nishanth Menon , Tero Kristo , Rob Herring , , , Subject: [PATCH v4 1/3] arm64: dts: ti: k3-j7200: Add gpio nodes Date: Thu, 28 Jan 2021 20:57:42 +0530 Message-ID: <20210128152744.12439-2-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210128152744.12439-1-a-govindraju@ti.com> References: <20210128152744.12439-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Faiz Abbas There are 4 instances of gpio modules in main domain: gpio0, gpio2, gpio4 and gpio6 Groups are created to provide protection between different processor virtual worlds. Each of these modules I/O pins are muxed within the group. Exactly one module can be selected to control the corresponding pin by selecting it in the pad mux configuration registers. This group pins out 69 lines (5 banks). Add DT modes for each module instance in the main domain. Similar to the gpio groups in main domain, there is one gpio group in wakeup domain with 2 mdoules instances in it. The gpio group pins out 73 pins (5 banks). Add DT nodes for each module instance in the wakeup domain. Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori Signed-off-by: Aswath Govindraju --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 72 +++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 34 +++++++++ 2 files changed, 106 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index d623004cfc9e..7a04a113f445 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -675,6 +675,78 @@ }; }; =20 + main_gpio0: gpio@600000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <145>, <146>, <147>, <148>, + <149>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <69>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 105 0>; + clock-names =3D "gpio"; + }; + + main_gpio2: gpio@610000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <154>, <155>, <156>, <157>, + <158>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <69>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 107 0>; + clock-names =3D "gpio"; + }; + + main_gpio4: gpio@620000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00620000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <163>, <164>, <165>, <166>, + <167>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <69>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 109 0>; + clock-names =3D "gpio"; + }; + + main_gpio6: gpio@630000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00630000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <172>, <173>, <174>, <175>, + <176>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <69>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 111 0>; + clock-names =3D "gpio"; + }; + main_r5fss0: r5fss@5c00000 { compatible =3D "ti,j7200-r5fss"; ti,cluster-mode =3D <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 0a8df7e4739c..3376bd57fd2d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -108,6 +108,40 @@ ti,interrupt-ranges =3D <16 960 16>; }; =20 + wkup_gpio0: gpio@42110000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x42110000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&wkup_gpio_intr>; + interrupts =3D <103>, <104>, <105>, <106>, <107>, <108>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <73>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 113 0>; + clock-names =3D "gpio"; + }; + + wkup_gpio1: gpio@42100000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x42100000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&wkup_gpio_intr>; + interrupts =3D <112>, <113>, <114>, <115>, <116>, <117>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <73>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 114 0>; + clock-names =3D "gpio"; + }; + mcu_navss: bus@28380000 { compatible =3D "simple-mfd"; #address-cells =3D <2>; --=20 2.17.1