From nobody Sat May 10 05:07:43 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=quarantine dis=quarantine) header.from=ti.com ARC-Seal: i=1; a=rsa-sha256; t=1611847877; cv=none; d=zohomail.com; s=zohoarc; b=QJ6bg5+k7W9kY0EBsrsFOsq6rBqwQrcQuktl5yH5dxMAejCxAy+qzWle67RWlMNAlvm0YSfyYBJLdnOKHu2K+VIivz/6+VJmlevh0nMiafQxwu64k1waGOs//8lhnH6r2aLxfspVoTpTWsIeeDJe8twQGv1ItXDxDgbBu3vb9RU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1611847877; h=Content-Type:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=jGXoJrXwMpqJe3qiwjtpPaGaJHxgdeTmxLm5Pjl+WJ0=; b=oKTjV5qLJ3GoI5g+tgW7+tffZ5gBzG9uzvh9VrsPhmLT/axC/UhH5Pg+6YqK07S7dweU/rHAS9IJ0bKFkYUScY+/7bqxVf1TTTiqe3LTVrC6lHSU1hzUWCSkKd3Os5lX42+Se7ff9SmH1BhNZqjz8CpJSsE6p+mg/o2tElv+Ai0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=quarantine dis=quarantine) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1611847877353805.9208239640305; Thu, 28 Jan 2021 07:31:17 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232095AbhA1Pai (ORCPT ); Thu, 28 Jan 2021 10:30:38 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35342 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231724AbhA1P3p (ORCPT ); Thu, 28 Jan 2021 10:29:45 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 10SFS6Cu074889; Thu, 28 Jan 2021 09:28:06 -0600 Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 10SFS6jM074702 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 28 Jan 2021 09:28:06 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 28 Jan 2021 09:28:06 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 28 Jan 2021 09:28:06 -0600 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 10SFRk5D094536; Thu, 28 Jan 2021 09:28:02 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1611847686; bh=jGXoJrXwMpqJe3qiwjtpPaGaJHxgdeTmxLm5Pjl+WJ0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BGdTPoiRzs2P5IeZ9W7/n/hh9cQu/o/P2nv9vwSQEZnUArnlA2PiIr7gr57BSmtkp nAPSwxM5PgQLIXNSeS7PrYxrzD6rlGE/kxzSxNAjc5nzfx5s9UCiEyXeQlMxu9EBSa P7ZM6SDVrXgAMZqBg3HflovPe9DP6WS4EdIpLO84= From: Aswath Govindraju CC: Lokesh Vutla , Vignesh Raghavendra , Kishon Vijay Abraham I , Sekhar Nori , Faiz Abbas , Aswath Govindraju , Nishanth Menon , Tero Kristo , Rob Herring , , , Subject: [PATCH v4 3/3] arm64: dts: ti: k3-j7200: Add support for higher speed modes in MMCSD subsystems Date: Thu, 28 Jan 2021 20:57:44 +0530 Message-ID: <20210128152744.12439-4-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210128152744.12439-1-a-govindraju@ti.com> References: <20210128152744.12439-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The following speed modes are now supported in J7200 SoC, - HS200 and HS400 modes at 1.8 V card voltage, in MMCSD0 subsystem [1]. - UHS-I speed modes in MMCSD1 subsystem [1]. Add support for UHS-I modes by adding voltage regulator device tree nodes and corresponding pinmux details, to power cycle and voltage switch cards. Also set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1 device tree nodes. [1] - section 12.3.6.1.1 MMCSD Features, in https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf Signed-off-by: Aswath Govindraju --- .../dts/ti/k3-j7200-common-proc-board.dts | 31 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 3 +- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 07d03ce05d9d..e670aaeb6c56 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -16,6 +16,29 @@ stdout-path =3D "serial2:115200n8"; bootargs =3D "console=3DttyS2,115200n8 earlycon=3Dns16550a,mmio32,0x0280= 0000"; }; + + vdd_mmc1: fixedregulator-sd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpios =3D <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: gpio-regulator-vdd-sd-dv { + compatible =3D "regulator-gpio"; + regulator-name =3D "vdd_sd_dv"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vdd_sd_dv_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + gpios =3D <&main_gpio0 55 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0 + 3300000 0x1>; + }; }; =20 &wkup_pmx0 { @@ -70,6 +93,12 @@ J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; }; + + vdd_sd_dv_pins_default: vdd_sd_dv_pins_default { + pinctrl-single,pins =3D < + J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ + >; + }; }; =20 &wkup_uart0 { @@ -206,6 +235,8 @@ /* SD card */ pinctrl-0 =3D <&main_mmc1_pins_default>; pinctrl-names =3D "default"; + vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vdd_sd_dv>; ti,driver-strength-ohm =3D <50>; disable-wp; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 7a04a113f445..c9877b24fbae 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -520,6 +520,8 @@ ti,trm-icp =3D <0x8>; bus-width =3D <8>; mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; dma-coherent; }; =20 @@ -537,7 +539,6 @@ ti,otap-del-sel-sdr50 =3D <0xc>; ti,otap-del-sel-sdr104 =3D <0x5>; ti,otap-del-sel-ddr50 =3D <0xc>; - no-1-8-v; dma-coherent; }; =20 --=20 2.17.1