From nobody Sat May 10 03:41:06 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612775985; cv=none; d=zohomail.com; s=zohoarc; b=MTQPTf9WQPATED858sGUJEyWY4IiRJLi2lUDwwvwf3vXXig2kULOtrpJr9k2dKcAB7FAM9VHYLmkxbXuXRMjnDAcQ3StuutrwdwWyF/3fyhYv91FvelAs2GPirGwjGHk+uwNzYGdZkXhhmWUvXHykXe2XhfuiNmiyT90pLed49k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612775985; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=yaq0RcImvgrycDNv4D66rk5ojPKzGNPlHlmaaOxhzmc=; b=kjqsJFYuo0OHi1ZGxOTJUM7b5Co3YfuacydEzIXU3/XCwdJNOZckHjz6SouChRMaoxFfGU/GruqSU8/H0xV/uO3JRBWlyxvRaPwSR4fiMD9g3ajeerzS6uqzar8YkfujIp/G44NnpobHQTr0J67KTU8wmiXC1Ibg+wo5c+JNtT4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1612775984942308.3332143923883; Mon, 8 Feb 2021 01:19:44 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231669AbhBHJTC (ORCPT ); Mon, 8 Feb 2021 04:19:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230155AbhBHJAz (ORCPT ); Mon, 8 Feb 2021 04:00:55 -0500 Received: from forward103o.mail.yandex.net (forward103o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::606]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CDD0C06178B; Mon, 8 Feb 2021 01:00:05 -0800 (PST) Received: from iva4-b3068118e41e.qloud-c.yandex.net (iva4-b3068118e41e.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:14a6:0:640:b306:8118]) by forward103o.mail.yandex.net (Yandex) with ESMTP id 503405F81F1B; Mon, 8 Feb 2021 12:00:02 +0300 (MSK) Received: from iva5-057a0d1fbbd8.qloud-c.yandex.net (iva5-057a0d1fbbd8.qloud-c.yandex.net [2a02:6b8:c0c:7f1c:0:640:57a:d1f]) by iva4-b3068118e41e.qloud-c.yandex.net (mxback/Yandex) with ESMTP id nPwFxhqqDr-02HacKlS; Mon, 08 Feb 2021 12:00:02 +0300 Received: by iva5-057a0d1fbbd8.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id N9nOuejTfy-01JmfV7W; Mon, 08 Feb 2021 12:00:01 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612774802; bh=yaq0RcImvgrycDNv4D66rk5ojPKzGNPlHlmaaOxhzmc=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=tUSui/dFcqaPG3691Z0i3APuaqIE7VisrxSqSaKeQJl9CJy9xrSqg6+R4lRe9AbSH FA+cDnGONI/64X9++coJLlzyQCyO7RgFWCVNdOHY/kqFiCMRwQcXl8jpdChgFG/qSa K5z8MbpSvGksPaTrcbRu7JmPMdGZFjpLAqqurQ7Q= Authentication-Results: iva4-b3068118e41e.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Bartosz Golaszewski , Alexander Sverdlin , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/7] gpio: ep93xx: fix BUG_ON port F usage Date: Mon, 8 Feb 2021 11:59:48 +0300 Message-Id: <20210208085954.30050-2-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208085954.30050-1-nikita.shubin@maquefel.me> References: <20210208085954.30050-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Two index spaces and ep93xx_gpio_port are confusing. Instead add a separate struct to store necessary data and remove ep93xx_gpio_port. - add struct to store IRQ related data for each IRQ capable chip - replace offset array with defined offsets - add IRQ registers offset for each IRQ capable chip into ep93xx_gpio_banks ------------[ cut here ]------------ kernel BUG at drivers/gpio/gpio-ep93xx.c:64! ---[ end trace 3f6544e133e9f5ae ]--- Fixes: fd935fc421e74 ("gpio: ep93xx: Do not pingpong irq numbers") Signed-off-by: Nikita Shubin --- v4->v5: - make to_ep93xx_gpio_irq_chip() static --- drivers/gpio/gpio-ep93xx.c | 186 ++++++++++++++++++++----------------- 1 file changed, 99 insertions(+), 87 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 226da8df6f10..64d6c2b4282e 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -25,6 +25,9 @@ /* Maximum value for gpio line identifiers */ #define EP93XX_GPIO_LINE_MAX 63 =20 +/* Number of GPIO chips in EP93XX */ +#define EP93XX_GPIO_CHIP_NUM 8 + /* Maximum value for irq capable line identifiers */ #define EP93XX_GPIO_LINE_MAX_IRQ 23 =20 @@ -34,74 +37,74 @@ */ #define EP93XX_GPIO_F_IRQ_BASE 80 =20 -struct ep93xx_gpio { - void __iomem *base; - struct gpio_chip gc[8]; +struct ep93xx_gpio_irq_chip { + u8 irq_offset; + u8 int_unmasked; + u8 int_enabled; + u8 int_type1; + u8 int_type2; + u8 int_debounce; }; =20 -/************************************************************************* - * Interrupt handling for EP93xx on-chip GPIOs - *************************************************************************/ -static unsigned char gpio_int_unmasked[3]; -static unsigned char gpio_int_enabled[3]; -static unsigned char gpio_int_type1[3]; -static unsigned char gpio_int_type2[3]; -static unsigned char gpio_int_debounce[3]; - -/* Port ordering is: A B F */ -static const u8 int_type1_register_offset[3] =3D { 0x90, 0xac, 0x4c }; -static const u8 int_type2_register_offset[3] =3D { 0x94, 0xb0, 0x50 }; -static const u8 eoi_register_offset[3] =3D { 0x98, 0xb4, 0x54 }; -static const u8 int_en_register_offset[3] =3D { 0x9c, 0xb8, 0x58 }; -static const u8 int_debounce_register_offset[3] =3D { 0xa8, 0xc4, 0x64 }; - -static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigne= d port) -{ - BUG_ON(port > 2); +struct ep93xx_gpio_chip { + struct gpio_chip gc; + struct ep93xx_gpio_irq_chip *eic; +}; =20 - writeb_relaxed(0, epg->base + int_en_register_offset[port]); +struct ep93xx_gpio { + void __iomem *base; + struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM]; +}; =20 - writeb_relaxed(gpio_int_type2[port], - epg->base + int_type2_register_offset[port]); +#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc) =20 - writeb_relaxed(gpio_int_type1[port], - epg->base + int_type1_register_offset[port]); +static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_ch= ip *gc) +{ + struct ep93xx_gpio_chip *egc =3D to_ep93xx_gpio_chip(gc); =20 - writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], - epg->base + int_en_register_offset[port]); + return egc->eic; } =20 -static int ep93xx_gpio_port(struct gpio_chip *gc) +/************************************************************************* + * Interrupt handling for EP93xx on-chip GPIOs + *************************************************************************/ +#define EP93XX_INT_TYPE1_OFFSET 0x00 +#define EP93XX_INT_TYPE2_OFFSET 0x04 +#define EP93XX_INT_EOI_OFFSET 0x08 +#define EP93XX_INT_EN_OFFSET 0x0c +#define EP93XX_INT_STATUS_OFFSET 0x10 +#define EP93XX_INT_RAW_STATUS_OFFSET 0x14 +#define EP93XX_INT_DEBOUNCE_OFFSET 0x18 + +static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, + struct ep93xx_gpio_irq_chip *eic) { - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D 0; + writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); =20 - while (port < ARRAY_SIZE(epg->gc) && gc !=3D &epg->gc[port]) - port++; + writeb_relaxed(eic->int_type2, + epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); =20 - /* This should not happen but is there as a last safeguard */ - if (port =3D=3D ARRAY_SIZE(epg->gc)) { - pr_crit("can't find the GPIO port\n"); - return 0; - } + writeb_relaxed(eic->int_type1, + epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); =20 - return port; + writeb_relaxed(eic->int_unmasked & eic->int_enabled, + epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); } =20 static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, unsigned int offset, bool enable) { struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); int port_mask =3D BIT(offset); =20 if (enable) - gpio_int_debounce[port] |=3D port_mask; + eic->int_debounce |=3D port_mask; else - gpio_int_debounce[port] &=3D ~port_mask; + eic->int_debounce &=3D ~port_mask; =20 - writeb(gpio_int_debounce[port], - epg->base + int_debounce_register_offset[port]); + writeb(eic->int_debounce, + epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET); } =20 static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) @@ -122,12 +125,12 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_des= c *desc) */ stat =3D readb(epg->base + EP93XX_GPIO_A_INT_STATUS); for_each_set_bit(offset, &stat, 8) - generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain, + generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain, offset)); =20 stat =3D readb(epg->base + EP93XX_GPIO_B_INT_STATUS); for_each_set_bit(offset, &stat, 8) - generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain, + generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain, offset)); =20 chained_irq_exit(irqchip, desc); @@ -153,52 +156,52 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc= *desc) static void ep93xx_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); int port_mask =3D BIT(d->irq & 7); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) { - gpio_int_type2[port] ^=3D port_mask; /* switch edge direction */ - ep93xx_gpio_update_int_params(epg, port); + eic->int_type2 ^=3D port_mask; /* switch edge direction */ + ep93xx_gpio_update_int_params(epg, eic); } =20 - writeb(port_mask, epg->base + eoi_register_offset[port]); + writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); } =20 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); int port_mask =3D BIT(d->irq & 7); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) - gpio_int_type2[port] ^=3D port_mask; /* switch edge direction */ + eic->int_type2 ^=3D port_mask; /* switch edge direction */ =20 - gpio_int_unmasked[port] &=3D ~port_mask; - ep93xx_gpio_update_int_params(epg, port); + eic->int_unmasked &=3D ~port_mask; + ep93xx_gpio_update_int_params(epg, eic); =20 - writeb(port_mask, epg->base + eoi_register_offset[port]); + writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); } =20 static void ep93xx_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); =20 - gpio_int_unmasked[port] &=3D ~BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, port); + eic->int_unmasked &=3D ~BIT(d->irq & 7); + ep93xx_gpio_update_int_params(epg, eic); } =20 static void ep93xx_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); =20 - gpio_int_unmasked[port] |=3D BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, port); + eic->int_unmasked |=3D BIT(d->irq & 7); + ep93xx_gpio_update_int_params(epg, eic); } =20 /* @@ -209,8 +212,8 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); int offset =3D d->irq & 7; int port_mask =3D BIT(offset); irq_flow_handler_t handler; @@ -219,32 +222,32 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, u= nsigned int type) =20 switch (type) { case IRQ_TYPE_EDGE_RISING: - gpio_int_type1[port] |=3D port_mask; - gpio_int_type2[port] |=3D port_mask; + eic->int_type1 |=3D port_mask; + eic->int_type2 |=3D port_mask; handler =3D handle_edge_irq; break; case IRQ_TYPE_EDGE_FALLING: - gpio_int_type1[port] |=3D port_mask; - gpio_int_type2[port] &=3D ~port_mask; + eic->int_type1 |=3D port_mask; + eic->int_type2 &=3D ~port_mask; handler =3D handle_edge_irq; break; case IRQ_TYPE_LEVEL_HIGH: - gpio_int_type1[port] &=3D ~port_mask; - gpio_int_type2[port] |=3D port_mask; + eic->int_type1 &=3D ~port_mask; + eic->int_type2 |=3D port_mask; handler =3D handle_level_irq; break; case IRQ_TYPE_LEVEL_LOW: - gpio_int_type1[port] &=3D ~port_mask; - gpio_int_type2[port] &=3D ~port_mask; + eic->int_type1 &=3D ~port_mask; + eic->int_type2 &=3D ~port_mask; handler =3D handle_level_irq; break; case IRQ_TYPE_EDGE_BOTH: - gpio_int_type1[port] |=3D port_mask; + eic->int_type1 |=3D port_mask; /* set initial polarity based on current input level */ if (gc->get(gc, offset)) - gpio_int_type2[port] &=3D ~port_mask; /* falling */ + eic->int_type2 &=3D ~port_mask; /* falling */ else - gpio_int_type2[port] |=3D port_mask; /* rising */ + eic->int_type2 |=3D port_mask; /* rising */ handler =3D handle_edge_irq; break; default: @@ -253,9 +256,9 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, uns= igned int type) =20 irq_set_handler_locked(d, handler); =20 - gpio_int_enabled[port] |=3D port_mask; + eic->int_enabled |=3D port_mask; =20 - ep93xx_gpio_update_int_params(epg, port); + ep93xx_gpio_update_int_params(epg, eic); =20 return 0; } @@ -276,17 +279,19 @@ struct ep93xx_gpio_bank { const char *label; int data; int dir; + int irq; int base; bool has_irq; bool has_hierarchical_irq; unsigned int irq_base; }; =20 -#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq, _has_hier, = _irq_base) \ +#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_= hier, _irq_base) \ { \ .label =3D _label, \ .data =3D _data, \ .dir =3D _dir, \ + .irq =3D _irq, \ .base =3D _base, \ .has_irq =3D _has_irq, \ .has_hierarchical_irq =3D _has_hier, \ @@ -295,16 +300,16 @@ struct ep93xx_gpio_bank { =20 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] =3D { /* Bank A has 8 IRQs */ - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true, false, 64), + EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64), /* Bank B has 8 IRQs */ - EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true, false, 72), - EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false, false, 0), - EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false, false, 0), - EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false, false, 0), + EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72), + EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0), + EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0), + EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0), /* Bank F has 8 IRQs */ - EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, false, true, 0), - EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false, false, 0), - EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false, false, 0), + EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0), + EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0), + EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0), }; =20 static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, @@ -326,13 +331,14 @@ static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc,= unsigned offset) return EP93XX_GPIO_F_IRQ_BASE + offset; } =20 -static int ep93xx_gpio_add_bank(struct gpio_chip *gc, +static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, struct platform_device *pdev, struct ep93xx_gpio *epg, struct ep93xx_gpio_bank *bank) { void __iomem *data =3D epg->base + bank->data; void __iomem *dir =3D epg->base + bank->dir; + struct gpio_chip *gc =3D &egc->gc; struct device *dev =3D &pdev->dev; struct gpio_irq_chip *girq; int err; @@ -347,6 +353,12 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, girq =3D &gc->irq; if (bank->has_irq || bank->has_hierarchical_irq) { gc->set_config =3D ep93xx_gpio_set_config; + egc->eic =3D devm_kcalloc(dev, 1, + sizeof(*egc->eic), + GFP_KERNEL); + if (!egc->eic) + return -ENOMEM; + egc->eic->irq_offset =3D bank->irq; girq->chip =3D &ep93xx_gpio_irq_chip; } =20 @@ -415,7 +427,7 @@ static int ep93xx_gpio_probe(struct platform_device *pd= ev) return PTR_ERR(epg->base); =20 for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { - struct gpio_chip *gc =3D &epg->gc[i]; + struct ep93xx_gpio_chip *gc =3D &epg->gc[i]; struct ep93xx_gpio_bank *bank =3D &ep93xx_gpio_banks[i]; =20 if (ep93xx_gpio_add_bank(gc, pdev, epg, bank)) --=20 2.26.2 From nobody Sat May 10 03:41:06 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612776235; cv=none; d=zohomail.com; s=zohoarc; b=Gid11DL6acxDnDUeVyTnmRHNfHyQ9MWhhnyTbWsXsTwjFrHS8wwVAJdrtiCd6orsk4o6ZuQsgDiexRKW0M99YoaDySf5t0a9zKLimdbiw4VZZlLiYTWPsU3Qb+z4xReKdl/JyA1JPNNj0dypoEfjo4wMzbiPHPC1mI1gL0My2Io= ARC-Message-Signature: i=1; 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Mon, 8 Feb 2021 04:00:47 -0500 Received: from forward105p.mail.yandex.net (forward105p.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:108]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8460AC061793; Mon, 8 Feb 2021 01:00:06 -0800 (PST) Received: from iva5-76c5c16f2a53.qloud-c.yandex.net (iva5-76c5c16f2a53.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:7bae:0:640:76c5:c16f]) by forward105p.mail.yandex.net (Yandex) with ESMTP id 39B8C4D414C9; Mon, 8 Feb 2021 12:00:03 +0300 (MSK) Received: from iva5-057a0d1fbbd8.qloud-c.yandex.net (iva5-057a0d1fbbd8.qloud-c.yandex.net [2a02:6b8:c0c:7f1c:0:640:57a:d1f]) by iva5-76c5c16f2a53.qloud-c.yandex.net (mxback/Yandex) with ESMTP id i4xTMfrdzM-03Fe1nL4; Mon, 08 Feb 2021 12:00:03 +0300 Received: by iva5-057a0d1fbbd8.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id N9nOuejTfy-02JmCtwL; Mon, 08 Feb 2021 12:00:02 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612774803; bh=hL8ZeV5eLJIrhOvSQrkOi9a1wUhtufNHtLYHQ8+odNU=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=FVyPm3t6s4vo8UCqiSBkTaJcxvrm+gb8OIkunbkJOaFwTIjFLeGpGO92CNV05mPJp CmruEefOZwr7H2XtYEvde+nBgompTLn3x4cDBfLceH4m+ij3/EmatOWi5iCo+f88ql 5AMNcDkNPYPSp+kp5kk4EUUjx8y6/Sbx7R+E+H0U= Authentication-Results: iva5-76c5c16f2a53.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Bartosz Golaszewski , Alexander Sverdlin , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/7] gpio: ep93xx: Fix single irqchip with multi gpiochips Date: Mon, 8 Feb 2021 11:59:49 +0300 Message-Id: <20210208085954.30050-3-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208085954.30050-1-nikita.shubin@maquefel.me> References: <20210208085954.30050-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Fixes the following warnings which results in interrupts disabled on port B/F: gpio gpiochip1: (B): detected irqchip that is shared with multiple gpiochip= s: please fix the driver. gpio gpiochip5: (F): detected irqchip that is shared with multiple gpiochip= s: please fix the driver. - added separate irqchip for each interrupt capable gpiochip - provided unique names for each irqchip Fixes: d2b091961510 ("gpio: ep93xx: Pass irqchip when adding gpiochip") Signed-off-by: Nikita Shubin --- v4->v5: - generate IRQ chip's names dynamicaly from label --- drivers/gpio/gpio-ep93xx.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 64d6c2b4282e..3d8eb8769470 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -38,6 +38,7 @@ #define EP93XX_GPIO_F_IRQ_BASE 80 =20 struct ep93xx_gpio_irq_chip { + struct irq_chip ic; u8 irq_offset; u8 int_unmasked; u8 int_enabled; @@ -331,6 +332,16 @@ static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, = unsigned offset) return EP93XX_GPIO_F_IRQ_BASE + offset; } =20 +static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic, = const char *label) +{ + ic->name =3D devm_kasprintf(dev, GFP_KERNEL, "gpio-irq-%s", label); + ic->irq_ack =3D ep93xx_gpio_irq_ack; + ic->irq_mask_ack =3D ep93xx_gpio_irq_mask_ack; + ic->irq_mask =3D ep93xx_gpio_irq_mask; + ic->irq_unmask =3D ep93xx_gpio_irq_unmask; + ic->irq_set_type =3D ep93xx_gpio_irq_type; +} + static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, struct platform_device *pdev, struct ep93xx_gpio *epg, @@ -352,6 +363,8 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, =20 girq =3D &gc->irq; if (bank->has_irq || bank->has_hierarchical_irq) { + struct irq_chip *ic; + gc->set_config =3D ep93xx_gpio_set_config; egc->eic =3D devm_kcalloc(dev, 1, sizeof(*egc->eic), @@ -359,7 +372,9 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, if (!egc->eic) return -ENOMEM; egc->eic->irq_offset =3D bank->irq; - girq->chip =3D &ep93xx_gpio_irq_chip; + ic =3D &egc->eic->ic; + ep93xx_init_irq_chip(dev, ic, bank->label); + girq->chip =3D ic; } =20 if (bank->has_irq) { --=20 2.26.2 From nobody Sat May 10 03:41:07 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612776290; cv=none; d=zohomail.com; s=zohoarc; b=dnV5iWyXG5X/LDNpzQuiBa+i0myyhbD/j2KYMMnNAEhu8gGpNTwKUzq5SvthlddcsBV50OU7sMPK4VcjEqKI7GadIhwF1Yg37OxNmGw94SD7LH5cIziVNnlp8T8nKwGyQxSETdL2gVB3aT++OMoQb4qsfAm3CBObZw2WUH9GpOo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Mon, 8 Feb 2021 04:00:47 -0500 Received: from forward106p.mail.yandex.net (forward106p.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:109]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19017C06178C; Mon, 8 Feb 2021 01:00:06 -0800 (PST) Received: from iva3-863a678c0048.qloud-c.yandex.net (iva3-863a678c0048.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:380:0:640:863a:678c]) by forward106p.mail.yandex.net (Yandex) with ESMTP id 1F6081C82902; Mon, 8 Feb 2021 12:00:04 +0300 (MSK) Received: from iva5-057a0d1fbbd8.qloud-c.yandex.net (iva5-057a0d1fbbd8.qloud-c.yandex.net [2a02:6b8:c0c:7f1c:0:640:57a:d1f]) by iva3-863a678c0048.qloud-c.yandex.net (mxback/Yandex) with ESMTP id eQZnP3ETh6-03HOaIIi; Mon, 08 Feb 2021 12:00:04 +0300 Received: by iva5-057a0d1fbbd8.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id N9nOuejTfy-03Jm76fA; Mon, 08 Feb 2021 12:00:03 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612774804; bh=TMVXM8lOITeIf4e94RQ4XSv0Ym1M40k+VpYRONppqTc=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=r6FdlVPJmHY2uDxlpxsS/ehgPm+yeNLAiP0q+UlfKBl26LUsS52g9VGH1VCEYYHmn K1uJCISbW7edCeTmD/zKFW0l+XoB/CKfauK3i7r0DSONvyGHfMMgF3Za8ltqx/p2Ti DgGWNROMG7YEkqd8Ke3juvOL1DdxiRXNKmBpGYg8= Authentication-Results: iva3-863a678c0048.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Alexander Sverdlin , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/7] gpio: ep93xx: Fix wrong irq numbers in port F Date: Mon, 8 Feb 2021 11:59:50 +0300 Message-Id: <20210208085954.30050-4-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208085954.30050-1-nikita.shubin@maquefel.me> References: <20210208085954.30050-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Port F IRQ's should be statically mapped to EP93XX_GPIO_F_IRQ_BASE. So we need to specify girq->first otherwise: "If device tree is used, then first_irq will be 0 and IRQ's get mapped dynamically on the fly" And that's not the thing we want. Reviewed-by: Linus Walleij Acked-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 3d8eb8769470..942da366220a 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -423,6 +423,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, girq->default_type =3D IRQ_TYPE_NONE; girq->handler =3D handle_level_irq; gc->to_irq =3D ep93xx_gpio_f_to_irq; + girq->first =3D EP93XX_GPIO_F_IRQ_BASE; } =20 return devm_gpiochip_add_data(dev, gc, epg); --=20 2.26.2 From nobody Sat May 10 03:41:07 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612776131; cv=none; d=zohomail.com; s=zohoarc; b=lt0uJf3D6CDfwTgI7wYkX/Kmyaz4iYHLG8C2IJioZTRq42NGPVBGWlchUCSMMcOPVUF+SDalbeVB8PatPUo42yHQooftjly+AqhBsJFxSpEy452Wdg7X4sDs7FbJrdBGJaDmmkSiEXXxwkn2FFbp/sLmTZonH9FOMJ9jLfKXkOg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612776131; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=kAj0mp7ZAXZrwLAHI3+98JSCy6v2QpaSUnUNgLKZJgw=; b=ZMnL4c2mwOWNqGsC7ybnVZdY74KKzeMSCDbRbMqjA4keEmmhbb/Sy7Xzsqie3R96jpiUTf53aEoal5bNWowqlXgzdutnh+Q/BrYoXoQYathtoBqwhXsyJ9hfTe6XZg4205I+AsycUSmNBkB7DK2KWLDdAouvUMKlG1xe6Ch7z48= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1612776131746176.79827170265742; Mon, 8 Feb 2021 01:22:11 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231302AbhBHJV6 (ORCPT ); Mon, 8 Feb 2021 04:21:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231293AbhBHJAu (ORCPT ); Mon, 8 Feb 2021 04:00:50 -0500 Received: from forward104p.mail.yandex.net (forward104p.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:107]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7752C061794; Mon, 8 Feb 2021 01:00:07 -0800 (PST) Received: from iva6-862b1c8daa54.qloud-c.yandex.net (iva6-862b1c8daa54.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:6107:0:640:862b:1c8d]) by forward104p.mail.yandex.net (Yandex) with ESMTP id 1F62B4B0277B; Mon, 8 Feb 2021 12:00:05 +0300 (MSK) Received: from iva5-057a0d1fbbd8.qloud-c.yandex.net (iva5-057a0d1fbbd8.qloud-c.yandex.net [2a02:6b8:c0c:7f1c:0:640:57a:d1f]) by iva6-862b1c8daa54.qloud-c.yandex.net (mxback/Yandex) with ESMTP id C3XTG39PHs-04Ga07VR; Mon, 08 Feb 2021 12:00:05 +0300 Received: by iva5-057a0d1fbbd8.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id N9nOuejTfy-04JmmF6Q; Mon, 08 Feb 2021 12:00:04 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612774805; bh=kAj0mp7ZAXZrwLAHI3+98JSCy6v2QpaSUnUNgLKZJgw=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=n2h/BE0HS4yE5iwpjDfJscxgz4ykXU/fPQ7FziGNhHr3nmxtktAjvUCjQ0Ln+f1+z fLXCtUjOft0TH10tAxUitH9eFgHcZY8G8gC/5WHHpWkYY9obHT8EsxHF4cfOkjXw/J wg8tjs3Mop55AugbaOMlmPfs5+v1Iw0K4+cuyqvw= Authentication-Results: iva6-862b1c8daa54.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Alexander Sverdlin , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 4/7] gpio: ep93xx: drop to_irq binding Date: Mon, 8 Feb 2021 11:59:51 +0300 Message-Id: <20210208085954.30050-5-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208085954.30050-1-nikita.shubin@maquefel.me> References: <20210208085954.30050-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" As ->to_irq is redefined in gpiochip_add_irqchip, having it defined in driver is useless, so let's drop it. Reviewed-by: Linus Walleij Acked-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 942da366220a..f8b21e1d55ed 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -327,11 +327,6 @@ static int ep93xx_gpio_set_config(struct gpio_chip *gc= , unsigned offset, return 0; } =20 -static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset) -{ - return EP93XX_GPIO_F_IRQ_BASE + offset; -} - static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic, = const char *label) { ic->name =3D devm_kasprintf(dev, GFP_KERNEL, "gpio-irq-%s", label); @@ -422,7 +417,6 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, } girq->default_type =3D IRQ_TYPE_NONE; girq->handler =3D handle_level_irq; - gc->to_irq =3D ep93xx_gpio_f_to_irq; girq->first =3D EP93XX_GPIO_F_IRQ_BASE; } =20 --=20 2.26.2 From nobody Sat May 10 03:41:07 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; 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Mon, 8 Feb 2021 12:00:06 +0300 (MSK) Received: from iva5-057a0d1fbbd8.qloud-c.yandex.net (iva5-057a0d1fbbd8.qloud-c.yandex.net [2a02:6b8:c0c:7f1c:0:640:57a:d1f]) by iva5-92838732ac93.qloud-c.yandex.net (mxback/Yandex) with ESMTP id ORo1Eve0am-05FiD2eC; Mon, 08 Feb 2021 12:00:05 +0300 Received: by iva5-057a0d1fbbd8.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id N9nOuejTfy-05JmNOnk; Mon, 08 Feb 2021 12:00:05 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612774806; bh=b/Ry2Xk9aF/rndRuF3W44rB8uOXHH3UAMyk1tmA0CIQ=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=Df0LmBi+Pm4n0AwzjNj/4+dnJB4juLVWMSS5wkM3dPxssIJDg3+3Tzaq82hbkj4LP qCFtA5Wyg3q5eUSlddR94N58DuJ96Y0G5MHwM52K83jSN8N29H54OpCStN7v5cverJ i9LIx2rth4K5LOdExgodHoutC+/VXbBvthSZ9J6s= Authentication-Results: iva5-92838732ac93.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Alexander Sverdlin , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 5/7] gpio: ep93xx: Fix typo s/hierarchial/hierarchical Date: Mon, 8 Feb 2021 11:59:52 +0300 Message-Id: <20210208085954.30050-6-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208085954.30050-1-nikita.shubin@maquefel.me> References: <20210208085954.30050-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Fix typo in comment. Reviewed-by: Linus Walleij Acked-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index f8b21e1d55ed..9ac8a8b830c1 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -395,7 +395,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, =20 /* * FIXME: convert this to use hierarchical IRQ support! - * this requires fixing the root irqchip to be hierarchial. + * this requires fixing the root irqchip to be hierarchical. */ girq->parent_handler =3D ep93xx_gpio_f_irq_handler; girq->num_parents =3D 8; --=20 2.26.2 From nobody Sat May 10 03:41:07 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; 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Mon, 8 Feb 2021 01:23:50 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231489AbhBHJWh (ORCPT ); Mon, 8 Feb 2021 04:22:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230174AbhBHJAu (ORCPT ); Mon, 8 Feb 2021 04:00:50 -0500 Received: from forward103o.mail.yandex.net (forward103o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::606]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC553C0617A7; Mon, 8 Feb 2021 01:00:08 -0800 (PST) Received: from iva3-4f441b146a71.qloud-c.yandex.net (iva3-4f441b146a71.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:498c:0:640:4f44:1b14]) by forward103o.mail.yandex.net (Yandex) with ESMTP id 26C445F82683; Mon, 8 Feb 2021 12:00:07 +0300 (MSK) Received: from iva5-057a0d1fbbd8.qloud-c.yandex.net (iva5-057a0d1fbbd8.qloud-c.yandex.net [2a02:6b8:c0c:7f1c:0:640:57a:d1f]) by iva3-4f441b146a71.qloud-c.yandex.net (mxback/Yandex) with ESMTP id 537mwW8XWl-06IWgjc3; Mon, 08 Feb 2021 12:00:07 +0300 Received: by iva5-057a0d1fbbd8.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id N9nOuejTfy-06JmU6jS; Mon, 08 Feb 2021 12:00:06 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612774807; bh=Dvew1cyWJB7ZvuR0min90f0IAtlia3k6CTMpUE02mQs=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=rm1yEwgGcBT57bCRzirWjiRr21wzo1JNQmrLeW68En+htxtJxVQ6g9XxryjLXyr2q 6IX88r0rW6XobBUYB+6I4yAUfNLTXso4NINdK6UwMEFCdiV5DYMIdPyWVX/LHtYF+2 a0khONknSlzw7ZAxa8kaCJgWHc91alQIKmGFSX58= Authentication-Results: iva3-4f441b146a71.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Alexander Sverdlin , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 6/7] gpio: ep93xx: refactor ep93xx_gpio_add_bank Date: Mon, 8 Feb 2021 11:59:53 +0300 Message-Id: <20210208085954.30050-7-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208085954.30050-1-nikita.shubin@maquefel.me> References: <20210208085954.30050-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" - replace plain numbers with girq->num_parents in devm_kcalloc - replace plain numbers with girq->num_parents for port F - refactor i - 1 to i + 1 to make loop more readable - combine getting IRQ's loop and setting handler's into single loop Reviewed-by: Linus Walleij Acked-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 9ac8a8b830c1..e75f7a9e40a0 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -377,7 +377,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, =20 girq->parent_handler =3D ep93xx_gpio_ab_irq_handler; girq->num_parents =3D 1; - girq->parents =3D devm_kcalloc(dev, 1, + girq->parents =3D devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) @@ -399,15 +399,14 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_ch= ip *egc, */ girq->parent_handler =3D ep93xx_gpio_f_irq_handler; girq->num_parents =3D 8; - girq->parents =3D devm_kcalloc(dev, 8, + girq->parents =3D devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) return -ENOMEM; /* Pick resources 1..8 for these IRQs */ - for (i =3D 1; i <=3D 8; i++) - girq->parents[i - 1] =3D platform_get_irq(pdev, i); - for (i =3D 0; i < 8; i++) { + for (i =3D 0; i < girq->num_parents; i++) { + girq->parents[i] =3D platform_get_irq(pdev, i + 1); gpio_irq =3D EP93XX_GPIO_F_IRQ_BASE + i; irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, --=20 2.26.2 From nobody Sat May 10 03:41:07 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; 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Mon, 08 Feb 2021 12:00:08 +0300 Received: by iva5-057a0d1fbbd8.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id N9nOuejTfy-07Jm5NWj; Mon, 08 Feb 2021 12:00:07 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612774808; bh=B0IIOt3cj9+Gh6aHiITYj112foxYpEHsZahL1VsljjM=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=Tj/JrZckxfM9Gpijf4UmNkR5Q032U29PDiJvMU9GlyYu9GYH5HDbe3EdrhO5QqE+c 9Q682bY4539OOXXTre+dhU9YiM3Tp9L1g4lgDL08IPUfQV/JBTz3LruAPcJ/B3rD4u YfOa3hc2ZA24bKyXxZZ1r/aOcZvkfgRu/owWQu6k= Authentication-Results: iva1-6891ef6bb416.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Alexander Sverdlin , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 7/7] gpio: ep93xx: refactor base IRQ number Date: Mon, 8 Feb 2021 11:59:54 +0300 Message-Id: <20210208085954.30050-8-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208085954.30050-1-nikita.shubin@maquefel.me> References: <20210208085954.30050-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" - use predefined constants instead of plain numbers - use provided bank IRQ number instead of defined constant for port F Reviewed-by: Linus Walleij Reviewed-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index e75f7a9e40a0..9cc2c2b4309f 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -31,6 +31,8 @@ /* Maximum value for irq capable line identifiers */ #define EP93XX_GPIO_LINE_MAX_IRQ 23 =20 +#define EP93XX_GPIO_A_IRQ_BASE 64 +#define EP93XX_GPIO_B_IRQ_BASE 72 /* * Static mapping of GPIO bank F IRQS: * F0..F7 (16..24) to irq 80..87. @@ -301,14 +303,14 @@ struct ep93xx_gpio_bank { =20 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] =3D { /* Bank A has 8 IRQs */ - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64), + EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ= _BASE), /* Bank B has 8 IRQs */ - EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72), + EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ= _BASE), EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0), EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0), EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0), /* Bank F has 8 IRQs */ - EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0), + EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IR= Q_BASE), EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0), EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0), }; @@ -407,7 +409,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, /* Pick resources 1..8 for these IRQs */ for (i =3D 0; i < girq->num_parents; i++) { girq->parents[i] =3D platform_get_irq(pdev, i + 1); - gpio_irq =3D EP93XX_GPIO_F_IRQ_BASE + i; + gpio_irq =3D bank->irq_base + i; irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, @@ -416,7 +418,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, } girq->default_type =3D IRQ_TYPE_NONE; girq->handler =3D handle_level_irq; - girq->first =3D EP93XX_GPIO_F_IRQ_BASE; + girq->first =3D bank->irq_base; } =20 return devm_gpiochip_add_data(dev, gc, epg); --=20 2.26.2