From nobody Sat May 10 00:19:22 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612877567; cv=none; d=zohomail.com; s=zohoarc; b=RB4mkxs5BNYkba2Ewfs7oJmz1T0NlK53ArQarIRDF9ZLx87gHIB8y3J7iQCrnwqQhrVgWageHipGvTwNtWMUcPYjpMskd9tWJT706K6jFE3OQslkdAtGZwRGt6PRTN0h3KjbeoCywcTuyLo3DFZHwIV5GlUkox+D+IqJyVSZ6Og= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612877567; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=fmwE/XgTerMLeKbUuKELRpwmcBrcLMo8ar0HxlX0N5U=; b=YTykBRMuy1BAN5WLpXL6xjAZ4UeCeduCHG/jkIj2SJXE+qEOwRD83rwMjlXbYCAJVBXGl2IHQyK2IXDDXf9MWLykjKwjdpuQiG0S4S7Z7QhFpskFhabgeGoFTHzVN74ZFJJdIBOUyZ2RepYTOIsnzdsQEgzqjAetGBMWkERTyx8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1612877567372636.763273446184; Tue, 9 Feb 2021 05:32:47 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231490AbhBINcb (ORCPT ); Tue, 9 Feb 2021 08:32:31 -0500 Received: from forward103p.mail.yandex.net ([77.88.28.106]:45159 "EHLO forward103p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230409AbhBINcH (ORCPT ); Tue, 9 Feb 2021 08:32:07 -0500 Received: from iva7-b0912e7c43b6.qloud-c.yandex.net (iva7-b0912e7c43b6.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:2e8e:0:640:b091:2e7c]) by forward103p.mail.yandex.net (Yandex) with ESMTP id 6280C18C0547; Tue, 9 Feb 2021 16:31:19 +0300 (MSK) Received: from iva1-bc1861525829.qloud-c.yandex.net (iva1-bc1861525829.qloud-c.yandex.net [2a02:6b8:c0c:a0e:0:640:bc18:6152]) by iva7-b0912e7c43b6.qloud-c.yandex.net (mxback/Yandex) with ESMTP id 69qirZ5sfO-VJISpMxQ; Tue, 09 Feb 2021 16:31:19 +0300 Received: by iva1-bc1861525829.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id aJNFhJtpP6-VIoaAKRi; Tue, 09 Feb 2021 16:31:18 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612877479; bh=fmwE/XgTerMLeKbUuKELRpwmcBrcLMo8ar0HxlX0N5U=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=jl7HYoJPjSonvXgDhd1bz6u5Tm5HL+FwvsuSKddsNJYqOuDlzR9P8M120h8SJkoSh xfZqViY6XhFNLeOn7jHTsp7WlWJwfSF/nLTiw7submS1B5zoGPYzJ8H25YrxI8acAn s9BJ+3/VPd3SRYCAwFhs27cFbdsowFYNXXDBa5VA= Authentication-Results: iva7-b0912e7c43b6.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Alexander Sverdlin , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/7] gpio: ep93xx: fix BUG_ON port F usage Date: Tue, 9 Feb 2021 16:31:04 +0300 Message-Id: <20210209133110.7383-2-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210209133110.7383-1-nikita.shubin@maquefel.me> References: <20210209133110.7383-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Two index spaces and ep93xx_gpio_port are confusing. Instead add a separate struct to store necessary data and remove ep93xx_gpio_port. - add struct to store IRQ related data for each IRQ capable chip - replace offset array with defined offsets - add IRQ registers offset for each IRQ capable chip into ep93xx_gpio_banks Reviewed-by: Alexander Sverdlin Tested-by: Alexander Sverdlin ------------[ cut here ]------------ kernel BUG at drivers/gpio/gpio-ep93xx.c:64! ---[ end trace 3f6544e133e9f5ae ]--- Fixes: fd935fc421e74 ("gpio: ep93xx: Do not pingpong irq numbers") Reviewed-by: Alexander Sverdlin Tested-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 186 ++++++++++++++++++++----------------- 1 file changed, 99 insertions(+), 87 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 226da8df6f10..64d6c2b4282e 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -25,6 +25,9 @@ /* Maximum value for gpio line identifiers */ #define EP93XX_GPIO_LINE_MAX 63 =20 +/* Number of GPIO chips in EP93XX */ +#define EP93XX_GPIO_CHIP_NUM 8 + /* Maximum value for irq capable line identifiers */ #define EP93XX_GPIO_LINE_MAX_IRQ 23 =20 @@ -34,74 +37,74 @@ */ #define EP93XX_GPIO_F_IRQ_BASE 80 =20 -struct ep93xx_gpio { - void __iomem *base; - struct gpio_chip gc[8]; +struct ep93xx_gpio_irq_chip { + u8 irq_offset; + u8 int_unmasked; + u8 int_enabled; + u8 int_type1; + u8 int_type2; + u8 int_debounce; }; =20 -/************************************************************************* - * Interrupt handling for EP93xx on-chip GPIOs - *************************************************************************/ -static unsigned char gpio_int_unmasked[3]; -static unsigned char gpio_int_enabled[3]; -static unsigned char gpio_int_type1[3]; -static unsigned char gpio_int_type2[3]; -static unsigned char gpio_int_debounce[3]; - -/* Port ordering is: A B F */ -static const u8 int_type1_register_offset[3] =3D { 0x90, 0xac, 0x4c }; -static const u8 int_type2_register_offset[3] =3D { 0x94, 0xb0, 0x50 }; -static const u8 eoi_register_offset[3] =3D { 0x98, 0xb4, 0x54 }; -static const u8 int_en_register_offset[3] =3D { 0x9c, 0xb8, 0x58 }; -static const u8 int_debounce_register_offset[3] =3D { 0xa8, 0xc4, 0x64 }; - -static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigne= d port) -{ - BUG_ON(port > 2); +struct ep93xx_gpio_chip { + struct gpio_chip gc; + struct ep93xx_gpio_irq_chip *eic; +}; =20 - writeb_relaxed(0, epg->base + int_en_register_offset[port]); +struct ep93xx_gpio { + void __iomem *base; + struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM]; +}; =20 - writeb_relaxed(gpio_int_type2[port], - epg->base + int_type2_register_offset[port]); +#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc) =20 - writeb_relaxed(gpio_int_type1[port], - epg->base + int_type1_register_offset[port]); +static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_ch= ip *gc) +{ + struct ep93xx_gpio_chip *egc =3D to_ep93xx_gpio_chip(gc); =20 - writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], - epg->base + int_en_register_offset[port]); + return egc->eic; } =20 -static int ep93xx_gpio_port(struct gpio_chip *gc) +/************************************************************************* + * Interrupt handling for EP93xx on-chip GPIOs + *************************************************************************/ +#define EP93XX_INT_TYPE1_OFFSET 0x00 +#define EP93XX_INT_TYPE2_OFFSET 0x04 +#define EP93XX_INT_EOI_OFFSET 0x08 +#define EP93XX_INT_EN_OFFSET 0x0c +#define EP93XX_INT_STATUS_OFFSET 0x10 +#define EP93XX_INT_RAW_STATUS_OFFSET 0x14 +#define EP93XX_INT_DEBOUNCE_OFFSET 0x18 + +static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, + struct ep93xx_gpio_irq_chip *eic) { - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D 0; + writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); =20 - while (port < ARRAY_SIZE(epg->gc) && gc !=3D &epg->gc[port]) - port++; + writeb_relaxed(eic->int_type2, + epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); =20 - /* This should not happen but is there as a last safeguard */ - if (port =3D=3D ARRAY_SIZE(epg->gc)) { - pr_crit("can't find the GPIO port\n"); - return 0; - } + writeb_relaxed(eic->int_type1, + epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); =20 - return port; + writeb_relaxed(eic->int_unmasked & eic->int_enabled, + epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); } =20 static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, unsigned int offset, bool enable) { struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); int port_mask =3D BIT(offset); =20 if (enable) - gpio_int_debounce[port] |=3D port_mask; + eic->int_debounce |=3D port_mask; else - gpio_int_debounce[port] &=3D ~port_mask; + eic->int_debounce &=3D ~port_mask; =20 - writeb(gpio_int_debounce[port], - epg->base + int_debounce_register_offset[port]); + writeb(eic->int_debounce, + epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET); } =20 static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) @@ -122,12 +125,12 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_des= c *desc) */ stat =3D readb(epg->base + EP93XX_GPIO_A_INT_STATUS); for_each_set_bit(offset, &stat, 8) - generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain, + generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain, offset)); =20 stat =3D readb(epg->base + EP93XX_GPIO_B_INT_STATUS); for_each_set_bit(offset, &stat, 8) - generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain, + generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain, offset)); =20 chained_irq_exit(irqchip, desc); @@ -153,52 +156,52 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc= *desc) static void ep93xx_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); int port_mask =3D BIT(d->irq & 7); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) { - gpio_int_type2[port] ^=3D port_mask; /* switch edge direction */ - ep93xx_gpio_update_int_params(epg, port); + eic->int_type2 ^=3D port_mask; /* switch edge direction */ + ep93xx_gpio_update_int_params(epg, eic); } =20 - writeb(port_mask, epg->base + eoi_register_offset[port]); + writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); } =20 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); int port_mask =3D BIT(d->irq & 7); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) - gpio_int_type2[port] ^=3D port_mask; /* switch edge direction */ + eic->int_type2 ^=3D port_mask; /* switch edge direction */ =20 - gpio_int_unmasked[port] &=3D ~port_mask; - ep93xx_gpio_update_int_params(epg, port); + eic->int_unmasked &=3D ~port_mask; + ep93xx_gpio_update_int_params(epg, eic); =20 - writeb(port_mask, epg->base + eoi_register_offset[port]); + writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); } =20 static void ep93xx_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); =20 - gpio_int_unmasked[port] &=3D ~BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, port); + eic->int_unmasked &=3D ~BIT(d->irq & 7); + ep93xx_gpio_update_int_params(epg, eic); } =20 static void ep93xx_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); =20 - gpio_int_unmasked[port] |=3D BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, port); + eic->int_unmasked |=3D BIT(d->irq & 7); + ep93xx_gpio_update_int_params(epg, eic); } =20 /* @@ -209,8 +212,8 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port =3D ep93xx_gpio_port(gc); int offset =3D d->irq & 7; int port_mask =3D BIT(offset); irq_flow_handler_t handler; @@ -219,32 +222,32 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, u= nsigned int type) =20 switch (type) { case IRQ_TYPE_EDGE_RISING: - gpio_int_type1[port] |=3D port_mask; - gpio_int_type2[port] |=3D port_mask; + eic->int_type1 |=3D port_mask; + eic->int_type2 |=3D port_mask; handler =3D handle_edge_irq; break; case IRQ_TYPE_EDGE_FALLING: - gpio_int_type1[port] |=3D port_mask; - gpio_int_type2[port] &=3D ~port_mask; + eic->int_type1 |=3D port_mask; + eic->int_type2 &=3D ~port_mask; handler =3D handle_edge_irq; break; case IRQ_TYPE_LEVEL_HIGH: - gpio_int_type1[port] &=3D ~port_mask; - gpio_int_type2[port] |=3D port_mask; + eic->int_type1 &=3D ~port_mask; + eic->int_type2 |=3D port_mask; handler =3D handle_level_irq; break; case IRQ_TYPE_LEVEL_LOW: - gpio_int_type1[port] &=3D ~port_mask; - gpio_int_type2[port] &=3D ~port_mask; + eic->int_type1 &=3D ~port_mask; + eic->int_type2 &=3D ~port_mask; handler =3D handle_level_irq; break; case IRQ_TYPE_EDGE_BOTH: - gpio_int_type1[port] |=3D port_mask; + eic->int_type1 |=3D port_mask; /* set initial polarity based on current input level */ if (gc->get(gc, offset)) - gpio_int_type2[port] &=3D ~port_mask; /* falling */ + eic->int_type2 &=3D ~port_mask; /* falling */ else - gpio_int_type2[port] |=3D port_mask; /* rising */ + eic->int_type2 |=3D port_mask; /* rising */ handler =3D handle_edge_irq; break; default: @@ -253,9 +256,9 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, uns= igned int type) =20 irq_set_handler_locked(d, handler); =20 - gpio_int_enabled[port] |=3D port_mask; + eic->int_enabled |=3D port_mask; =20 - ep93xx_gpio_update_int_params(epg, port); + ep93xx_gpio_update_int_params(epg, eic); =20 return 0; } @@ -276,17 +279,19 @@ struct ep93xx_gpio_bank { const char *label; int data; int dir; + int irq; int base; bool has_irq; bool has_hierarchical_irq; unsigned int irq_base; }; =20 -#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq, _has_hier, = _irq_base) \ +#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_= hier, _irq_base) \ { \ .label =3D _label, \ .data =3D _data, \ .dir =3D _dir, \ + .irq =3D _irq, \ .base =3D _base, \ .has_irq =3D _has_irq, \ .has_hierarchical_irq =3D _has_hier, \ @@ -295,16 +300,16 @@ struct ep93xx_gpio_bank { =20 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] =3D { /* Bank A has 8 IRQs */ - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true, false, 64), + EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64), /* Bank B has 8 IRQs */ - EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true, false, 72), - EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false, false, 0), - EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false, false, 0), - EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false, false, 0), + EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72), + EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0), + EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0), + EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0), /* Bank F has 8 IRQs */ - EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, false, true, 0), - EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false, false, 0), - EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false, false, 0), + EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0), + EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0), + EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0), }; =20 static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, @@ -326,13 +331,14 @@ static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc,= unsigned offset) return EP93XX_GPIO_F_IRQ_BASE + offset; } =20 -static int ep93xx_gpio_add_bank(struct gpio_chip *gc, +static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, struct platform_device *pdev, struct ep93xx_gpio *epg, struct ep93xx_gpio_bank *bank) { void __iomem *data =3D epg->base + bank->data; void __iomem *dir =3D epg->base + bank->dir; + struct gpio_chip *gc =3D &egc->gc; struct device *dev =3D &pdev->dev; struct gpio_irq_chip *girq; int err; @@ -347,6 +353,12 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, girq =3D &gc->irq; if (bank->has_irq || bank->has_hierarchical_irq) { gc->set_config =3D ep93xx_gpio_set_config; + egc->eic =3D devm_kcalloc(dev, 1, + sizeof(*egc->eic), + GFP_KERNEL); + if (!egc->eic) + return -ENOMEM; + egc->eic->irq_offset =3D bank->irq; girq->chip =3D &ep93xx_gpio_irq_chip; } =20 @@ -415,7 +427,7 @@ static int ep93xx_gpio_probe(struct platform_device *pd= ev) return PTR_ERR(epg->base); =20 for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { - struct gpio_chip *gc =3D &epg->gc[i]; + struct ep93xx_gpio_chip *gc =3D &epg->gc[i]; struct ep93xx_gpio_bank *bank =3D &ep93xx_gpio_banks[i]; =20 if (ep93xx_gpio_add_bank(gc, pdev, epg, bank)) --=20 2.26.2 From nobody Sat May 10 00:19:22 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612877566; cv=none; d=zohomail.com; s=zohoarc; b=l87YHpUqYX7Q47AwHcnjdMG4Oi4kbxb7Rr8fnQZrRoWD5LYWKGlBtC+SN8hvklBAa6YVk29CwVox46/So3KF7SLRhIrNteIJz++CS989UgpVHw6mCWlvtg05YzqAXQ8J0IzBoRqplG2Zv9hasu5ohFey46+9A5zx8WypNLybAOM= ARC-Message-Signature: i=1; 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Tue, 9 Feb 2021 08:32:04 -0500 Received: from forward103o.mail.yandex.net (forward103o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::606]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2940AC061786; Tue, 9 Feb 2021 05:31:23 -0800 (PST) Received: from iva5-9febf89e551b.qloud-c.yandex.net (iva5-9febf89e551b.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:7a23:0:640:9feb:f89e]) by forward103o.mail.yandex.net (Yandex) with ESMTP id 276295F80763; Tue, 9 Feb 2021 16:31:21 +0300 (MSK) Received: from iva1-bc1861525829.qloud-c.yandex.net (iva1-bc1861525829.qloud-c.yandex.net [2a02:6b8:c0c:a0e:0:640:bc18:6152]) by iva5-9febf89e551b.qloud-c.yandex.net (mxback/Yandex) with ESMTP id SBE1yoU5u7-VKI0pqlp; Tue, 09 Feb 2021 16:31:20 +0300 Received: by iva1-bc1861525829.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id aJNFhJtpP6-VKoaXPQY; Tue, 09 Feb 2021 16:31:20 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612877480; bh=oSCxM0stiR+3f2VqYJDegwfWeztBw98XkBlyFoS19sc=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=M3UVir7RjgYkpCYvBZeYrMsET+gPNVzsltyCrwSyDRqB4LvJ7WPSSfCFc/gKZPVBr SREdYUTClKrdvn7qQgxwO9Yb4j7ebcRfslVdcIHC10WtNP4aOXpBK8hNs/gxQ4838K +fNKzENBf7Tsdef0OZnussQgUO3wGiMSuiHlIZ84= Authentication-Results: iva5-9febf89e551b.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Bartosz Golaszewski , Alexander Sverdlin , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 2/7] gpio: ep93xx: Fix single irqchip with multi gpiochips Date: Tue, 9 Feb 2021 16:31:05 +0300 Message-Id: <20210209133110.7383-3-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210209133110.7383-1-nikita.shubin@maquefel.me> References: <20210209133110.7383-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Fixes the following warnings which results in interrupts disabled on port B/F: gpio gpiochip1: (B): detected irqchip that is shared with multiple gpiochip= s: please fix the driver. gpio gpiochip5: (F): detected irqchip that is shared with multiple gpiochip= s: please fix the driver. - added separate irqchip for each interrupt capable gpiochip - provided unique names for each irqchip Fixes: d2b091961510 ("gpio: ep93xx: Pass irqchip when adding gpiochip") Signed-off-by: Nikita Shubin --- v5->v6: - add devm_kasprintf() return value check and move it out from=20 ep93xx_init_irq_chip() - removed ep93xx_gpio_irq_chip - pass girq->chip instead of removed ep93xx_gpio_irq_chip to irq_set_chip_and_handler for port F --- drivers/gpio/gpio-ep93xx.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 64d6c2b4282e..94d9fa0d6aa7 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -38,6 +38,7 @@ #define EP93XX_GPIO_F_IRQ_BASE 80 =20 struct ep93xx_gpio_irq_chip { + struct irq_chip ic; u8 irq_offset; u8 int_unmasked; u8 int_enabled; @@ -263,15 +264,6 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, un= signed int type) return 0; } =20 -static struct irq_chip ep93xx_gpio_irq_chip =3D { - .name =3D "GPIO", - .irq_ack =3D ep93xx_gpio_irq_ack, - .irq_mask_ack =3D ep93xx_gpio_irq_mask_ack, - .irq_mask =3D ep93xx_gpio_irq_mask, - .irq_unmask =3D ep93xx_gpio_irq_unmask, - .irq_set_type =3D ep93xx_gpio_irq_type, -}; - /************************************************************************* * gpiolib interface for EP93xx on-chip GPIOs *************************************************************************/ @@ -331,6 +323,15 @@ static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, = unsigned offset) return EP93XX_GPIO_F_IRQ_BASE + offset; } =20 +static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic) +{ + ic->irq_ack =3D ep93xx_gpio_irq_ack; + ic->irq_mask_ack =3D ep93xx_gpio_irq_mask_ack; + ic->irq_mask =3D ep93xx_gpio_irq_mask; + ic->irq_unmask =3D ep93xx_gpio_irq_unmask; + ic->irq_set_type =3D ep93xx_gpio_irq_type; +} + static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, struct platform_device *pdev, struct ep93xx_gpio *epg, @@ -352,6 +353,8 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, =20 girq =3D &gc->irq; if (bank->has_irq || bank->has_hierarchical_irq) { + struct irq_chip *ic; + gc->set_config =3D ep93xx_gpio_set_config; egc->eic =3D devm_kcalloc(dev, 1, sizeof(*egc->eic), @@ -359,7 +362,12 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chi= p *egc, if (!egc->eic) return -ENOMEM; egc->eic->irq_offset =3D bank->irq; - girq->chip =3D &ep93xx_gpio_irq_chip; + ic =3D &egc->eic->ic; + ic->name =3D devm_kasprintf(dev, GFP_KERNEL, "gpio-irq-%s", bank->label); + if (!ic->name) + return -ENOMEM; + ep93xx_init_irq_chip(dev, ic); + girq->chip =3D ic; } =20 if (bank->has_irq) { @@ -401,7 +409,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, gpio_irq =3D EP93XX_GPIO_F_IRQ_BASE + i; irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, - &ep93xx_gpio_irq_chip, + girq->chip, handle_level_irq); irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); } --=20 2.26.2 From nobody Sat May 10 00:19:22 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612877566; cv=none; d=zohomail.com; s=zohoarc; b=G2ZpaEYdeyQJfg31IofjJwQ+MZuCky0LFdLgBCVqdJSWDKBdEGVQRYU36H/zadW3+QP/ktPpNdsjsRmNeLtW/1MuFL/6n3Xhst4P4ysDHIgRjm1CRWw5F8/O1G1n93CqySaR+lRRggKIPhgPJQH9UoiHHRRJHVnzmQQuP8GWQT4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612877566; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; 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Tue, 9 Feb 2021 16:31:22 +0300 (MSK) Received: from iva1-bc1861525829.qloud-c.yandex.net (iva1-bc1861525829.qloud-c.yandex.net [2a02:6b8:c0c:a0e:0:640:bc18:6152]) by iva8-f240adbdb32e.qloud-c.yandex.net (mxback/Yandex) with ESMTP id LxUrp0zlDJ-VLHaWaEY; Tue, 09 Feb 2021 16:31:21 +0300 Received: by iva1-bc1861525829.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id aJNFhJtpP6-VLoaIiCG; Tue, 09 Feb 2021 16:31:21 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612877481; bh=lduRyAoxgIxVCQylqzBQTH5yxMhYzLooO1actsXv0Zw=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=oL3DjYHxhTQ4LDWWRt3fqlJc9jsGukxLvaI2EN/TyVzrhtq7QYrvna+1hiVsV4EZX 4ZFP3/3LVUmZR18oJpcjXepC3mPh6CzTt2vAhzZKYW+DYWobZpmpmSFNyFKxmx9NTK Lksw5woq70189/arxsZDH79LgwYVKJ43gCGJ92B0= Authentication-Results: iva8-f240adbdb32e.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Alexander Sverdlin , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/7] gpio: ep93xx: Fix wrong irq numbers in port F Date: Tue, 9 Feb 2021 16:31:06 +0300 Message-Id: <20210209133110.7383-4-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210209133110.7383-1-nikita.shubin@maquefel.me> References: <20210209133110.7383-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Port F IRQ's should be statically mapped to EP93XX_GPIO_F_IRQ_BASE. So we need to specify girq->first otherwise: "If device tree is used, then first_irq will be 0 and IRQ's get mapped dynamically on the fly" And that's not the thing we want. Reviewed-by: Linus Walleij Acked-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 94d9fa0d6aa7..3dea4ce929ab 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -416,6 +416,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, girq->default_type =3D IRQ_TYPE_NONE; girq->handler =3D handle_level_irq; gc->to_irq =3D ep93xx_gpio_f_to_irq; + girq->first =3D EP93XX_GPIO_F_IRQ_BASE; } =20 return devm_gpiochip_add_data(dev, gc, epg); --=20 2.26.2 From nobody Sat May 10 00:19:22 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612877567; cv=none; d=zohomail.com; s=zohoarc; b=gA2RkYcPcQ/qmZADI+oQy1yY3Lmyu+y4E1vRcbdjhLlxJ2kjAhn659I/JMJuRQ1ED/aL87/bwRTCoItzpGGFZzOCaMW2RonjE/p4mHuMkGVDhxQtd8kLdbd2e8LglKebiKPMxzvpkMHaoH+RBTy0nPQ7uQjiytS6ofHM2pmypl4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612877567; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=6S6Er/Wd3A9qOjKgdKrJomCOg7AI6A4lzn/1huv+h7A=; b=PXLm/WjMHx4EEjSKj0mmEY8haCSmgTUQM2zOZRAttkqWotYSVbxM5Y4jQBOAcFOfAO7StRDeljsPqDd3QHIixAIknuPQtpZDx/EO8TcpzXuLFA8NbMd91+586OyirXCxzPjRw84NTliVn4YhaSSJx/nqd9YLiHtAzVeUb/jSOCE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1612877567004762.0206509458608; Tue, 9 Feb 2021 05:32:47 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231445AbhBINcX (ORCPT ); Tue, 9 Feb 2021 08:32:23 -0500 Received: from forward104o.mail.yandex.net ([37.140.190.179]:38372 "EHLO forward104o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231290AbhBINcH (ORCPT ); Tue, 9 Feb 2021 08:32:07 -0500 Received: from iva7-79032ba5307a.qloud-c.yandex.net (iva7-79032ba5307a.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:320d:0:640:7903:2ba5]) by forward104o.mail.yandex.net (Yandex) with ESMTP id DF251940841; Tue, 9 Feb 2021 16:31:22 +0300 (MSK) Received: from iva1-bc1861525829.qloud-c.yandex.net (iva1-bc1861525829.qloud-c.yandex.net [2a02:6b8:c0c:a0e:0:640:bc18:6152]) by iva7-79032ba5307a.qloud-c.yandex.net (mxback/Yandex) with ESMTP id 4xUL0yc1Kv-VMHuFLAD; Tue, 09 Feb 2021 16:31:22 +0300 Received: by iva1-bc1861525829.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id aJNFhJtpP6-VMoaSXTp; Tue, 09 Feb 2021 16:31:22 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612877482; bh=6S6Er/Wd3A9qOjKgdKrJomCOg7AI6A4lzn/1huv+h7A=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=YVHSsBpFM4D9avKnHedyXb1ghhuxR5pJP3rXoMAapSBh2etQoajEjp1wREfbi4qmQ YXgQWUpz6PRRLuVIHrAC96qkjPOQHGZKaQX24hUONW/xrrFu5WPJQHO9+3rov+zu5a bDFoTXbpD9/VN/+lruRhBiHY3S3KuK88lK36dy8Q= Authentication-Results: iva7-79032ba5307a.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Alexander Sverdlin , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/7] gpio: ep93xx: drop to_irq binding Date: Tue, 9 Feb 2021 16:31:07 +0300 Message-Id: <20210209133110.7383-5-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210209133110.7383-1-nikita.shubin@maquefel.me> References: <20210209133110.7383-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" As ->to_irq is redefined in gpiochip_add_irqchip, having it defined in driver is useless, so let's drop it. Reviewed-by: Linus Walleij Acked-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 3dea4ce929ab..a69bf3100f99 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -318,11 +318,6 @@ static int ep93xx_gpio_set_config(struct gpio_chip *gc= , unsigned offset, return 0; } =20 -static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset) -{ - return EP93XX_GPIO_F_IRQ_BASE + offset; -} - static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic) { ic->irq_ack =3D ep93xx_gpio_irq_ack; @@ -415,7 +410,6 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, } girq->default_type =3D IRQ_TYPE_NONE; girq->handler =3D handle_level_irq; - gc->to_irq =3D ep93xx_gpio_f_to_irq; girq->first =3D EP93XX_GPIO_F_IRQ_BASE; } =20 --=20 2.26.2 From nobody Sat May 10 00:19:22 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612877567; cv=none; d=zohomail.com; s=zohoarc; b=IRd2pe1pqucV+JHg6lAixsCERzHIQe4Xgi/41epfWMPcXB6k7+/iUt7XqBROx2K0SwFlY+lu4e7U1JQ+dDZTHKbyG0/cwpR9HNA37usWMo3rR5+EAyfmVGV/u65cNpaiTEZr7/BkUEVRDV731l3p7kw5pH3qBp92WrAGv4w79aA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612877567; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=dElC7nQ0BytxegF4+XkB3bMQiY+WpMtoh8a2xZVnmdw=; b=JMqLiBQpZpCx5HAbdahN3p4hJvzb24hNPAfuTDo9ptd1MadChIZQCucNJnora6g+R3wlLesetiCXKbvJwbC0nOWB5wEEaWhtPRR8CVOmdjO+yCmeB55mwok8owzFZHaCFOcFd7F0NHxv2Xq0z/DBcMAwb9VqS3DIBV4GFG6dCqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1612877567842627.7181942621042; Tue, 9 Feb 2021 05:32:47 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231520AbhBINcn (ORCPT ); Tue, 9 Feb 2021 08:32:43 -0500 Received: from forward103o.mail.yandex.net ([37.140.190.177]:58821 "EHLO forward103o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231292AbhBINcH (ORCPT ); Tue, 9 Feb 2021 08:32:07 -0500 Received: from iva6-b9aa172731b6.qloud-c.yandex.net (iva6-b9aa172731b6.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:9a88:0:640:b9aa:1727]) by forward103o.mail.yandex.net (Yandex) with ESMTP id C54815F80737; Tue, 9 Feb 2021 16:31:23 +0300 (MSK) Received: from iva1-bc1861525829.qloud-c.yandex.net (iva1-bc1861525829.qloud-c.yandex.net [2a02:6b8:c0c:a0e:0:640:bc18:6152]) by iva6-b9aa172731b6.qloud-c.yandex.net (mxback/Yandex) with ESMTP id 7x2E8nHkeE-VNIuLRIg; Tue, 09 Feb 2021 16:31:23 +0300 Received: by iva1-bc1861525829.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id aJNFhJtpP6-VNoas7eL; Tue, 09 Feb 2021 16:31:23 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612877483; bh=dElC7nQ0BytxegF4+XkB3bMQiY+WpMtoh8a2xZVnmdw=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=ICD3iVystfjcZxfTtjwYjbfUySrWT2Uth3SDLL91OqO7IK6wRIGwUk8GQqmoJ2ao8 eF2JYboZjSwvXxA8vAfjrghIvmb2HQsIUWd1SDleRhhD1z9FKu2eUhf7nNfj2MDTX0 hL/OqKNfiJ+eZibeWJGEAjHkY6WtWBbLkiYW6anw= Authentication-Results: iva6-b9aa172731b6.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Alexander Sverdlin , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 5/7] gpio: ep93xx: Fix typo s/hierarchial/hierarchical Date: Tue, 9 Feb 2021 16:31:08 +0300 Message-Id: <20210209133110.7383-6-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210209133110.7383-1-nikita.shubin@maquefel.me> References: <20210209133110.7383-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Fix typo in comment. Reviewed-by: Linus Walleij Acked-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index a69bf3100f99..9760df7d1172 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -388,7 +388,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, =20 /* * FIXME: convert this to use hierarchical IRQ support! - * this requires fixing the root irqchip to be hierarchial. + * this requires fixing the root irqchip to be hierarchical. */ girq->parent_handler =3D ep93xx_gpio_f_irq_handler; girq->num_parents =3D 8; --=20 2.26.2 From nobody Sat May 10 00:19:22 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; 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Tue, 9 Feb 2021 05:33:25 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231292AbhBINcq (ORCPT ); Tue, 9 Feb 2021 08:32:46 -0500 Received: from forward104o.mail.yandex.net ([37.140.190.179]:38428 "EHLO forward104o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231327AbhBINcJ (ORCPT ); Tue, 9 Feb 2021 08:32:09 -0500 Received: from iva4-66d7931d4d60.qloud-c.yandex.net (iva4-66d7931d4d60.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:78a3:0:640:66d7:931d]) by forward104o.mail.yandex.net (Yandex) with ESMTP id B987F940876; Tue, 9 Feb 2021 16:31:24 +0300 (MSK) Received: from iva1-bc1861525829.qloud-c.yandex.net (iva1-bc1861525829.qloud-c.yandex.net [2a02:6b8:c0c:a0e:0:640:bc18:6152]) by iva4-66d7931d4d60.qloud-c.yandex.net (mxback/Yandex) with ESMTP id tQU3zPfplQ-VOIaxjde; Tue, 09 Feb 2021 16:31:24 +0300 Received: by iva1-bc1861525829.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id aJNFhJtpP6-VNoaSKwt; Tue, 09 Feb 2021 16:31:24 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612877484; bh=aJvzXXLz8Fe5HdokcQEWZcrpg+/kk5XCdinRvVVSvP4=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=thjhnJg1IOd+MXkVZ5VQNHZZWD57de2StTVnntOMKdMyDWbrB1V2DakCJs1zs5xTk yHJvldOB4EMB70QK3I1+JE7585iUvNbgAnDXl0xxkJCecOOQyT/nC3F2/uhMSrz9Ri KLDysrLBbSWSw/OhsItKwAaU2LHnlj0BfMMtbrXI= Authentication-Results: iva4-66d7931d4d60.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Alexander Sverdlin , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 6/7] gpio: ep93xx: refactor ep93xx_gpio_add_bank Date: Tue, 9 Feb 2021 16:31:09 +0300 Message-Id: <20210209133110.7383-7-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210209133110.7383-1-nikita.shubin@maquefel.me> References: <20210209133110.7383-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" - replace plain numbers with girq->num_parents in devm_kcalloc - replace plain numbers with girq->num_parents for port F - refactor i - 1 to i + 1 to make loop more readable - combine getting IRQ's loop and setting handler's into single loop Reviewed-by: Linus Walleij Acked-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 9760df7d1172..56ddf6b9baba 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -370,7 +370,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, =20 girq->parent_handler =3D ep93xx_gpio_ab_irq_handler; girq->num_parents =3D 1; - girq->parents =3D devm_kcalloc(dev, 1, + girq->parents =3D devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) @@ -392,15 +392,14 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_ch= ip *egc, */ girq->parent_handler =3D ep93xx_gpio_f_irq_handler; girq->num_parents =3D 8; - girq->parents =3D devm_kcalloc(dev, 8, + girq->parents =3D devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) return -ENOMEM; /* Pick resources 1..8 for these IRQs */ - for (i =3D 1; i <=3D 8; i++) - girq->parents[i - 1] =3D platform_get_irq(pdev, i); - for (i =3D 0; i < 8; i++) { + for (i =3D 0; i < girq->num_parents; i++) { + girq->parents[i] =3D platform_get_irq(pdev, i + 1); gpio_irq =3D EP93XX_GPIO_F_IRQ_BASE + i; irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, --=20 2.26.2 From nobody Sat May 10 00:19:22 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612877485; bh=+/uxnxwE2Nyf3yhoKeSMi41J9tcJnV5GDK4jB7MzCqk=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=XBkb8WvD78ej/4a1PrX/F3/oEXLYtlvP/iuJYODq0BlhTswJ5dAEq/em2i6aLhJsT NGmVhzhExTMwJIKpuq03pHPAkcAokB0miGpLEzWOBD0LH1iHJ1bnFA4pGdl0JdG9mJ /I4EB9IWfxpER5rclsS/w2fUozrrgXNSj5H0MUdU= Authentication-Results: iva8-6377ea28ef3a.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Alexander Sverdlin , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 7/7] gpio: ep93xx: refactor base IRQ number Date: Tue, 9 Feb 2021 16:31:10 +0300 Message-Id: <20210209133110.7383-8-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210209133110.7383-1-nikita.shubin@maquefel.me> References: <20210209133110.7383-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" - use predefined constants instead of plain numbers - use provided bank IRQ number instead of defined constant for port F Reviewed-by: Linus Walleij Reviewed-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 56ddf6b9baba..ef148b26b587 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -31,6 +31,8 @@ /* Maximum value for irq capable line identifiers */ #define EP93XX_GPIO_LINE_MAX_IRQ 23 =20 +#define EP93XX_GPIO_A_IRQ_BASE 64 +#define EP93XX_GPIO_B_IRQ_BASE 72 /* * Static mapping of GPIO bank F IRQS: * F0..F7 (16..24) to irq 80..87. @@ -292,14 +294,14 @@ struct ep93xx_gpio_bank { =20 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] =3D { /* Bank A has 8 IRQs */ - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64), + EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ= _BASE), /* Bank B has 8 IRQs */ - EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72), + EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ= _BASE), EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0), EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0), EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0), /* Bank F has 8 IRQs */ - EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0), + EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IR= Q_BASE), EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0), EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0), }; @@ -400,7 +402,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, /* Pick resources 1..8 for these IRQs */ for (i =3D 0; i < girq->num_parents; i++) { girq->parents[i] =3D platform_get_irq(pdev, i + 1); - gpio_irq =3D EP93XX_GPIO_F_IRQ_BASE + i; + gpio_irq =3D bank->irq_base + i; irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, girq->chip, @@ -409,7 +411,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip= *egc, } girq->default_type =3D IRQ_TYPE_NONE; girq->handler =3D handle_level_irq; - girq->first =3D EP93XX_GPIO_F_IRQ_BASE; + girq->first =3D bank->irq_base; } =20 return devm_gpiochip_add_data(dev, gc, epg); --=20 2.26.2