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Mon, 15 Mar 2021 20:50:31 -0700 (PDT) From: Jiuyang Liu Cc: Andrew Waterman , Jiuyang Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Andrew Morton , Mike Rapoport , Kefeng Wang , Zong Li , Greentime Hu , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV Date: Tue, 16 Mar 2021 03:46:36 +0000 Message-Id: <20210316034638.16276-1-liu@jiuyang.me> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210316015328.13516-1-liu@jiuyang.me> References: <20210316015328.13516-1-liu@jiuyang.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This patch inserts SFENCE.VMA after modifying PTE based on RISC-V specification. arch/riscv/include/asm/pgtable.h: 1. implement pte_user, pte_global and pte_leaf to check correspond attribute of a pte_t. 2. insert SFENCE.VMA in set_pte_at based on RISC-V Volume 2, Privileged Spec v. 20190608 page 66 and 67: If software modifies a non-leaf PTE, it should execute SFENCE.VMA with rs1=3Dx0. If any PTE along the traversal path had its G bit set, rs2 must be x0; otherwise, rs2 should be set to the ASID for which the translation is being modified. If software modifies a leaf PTE, it should execute SFENCE.VMA with rs1 set to a virtual address within the page. If any PTE along the traversal path had its G bit set, rs2 must be x0; otherwise, rs2 should be set to the ASID for which the translation is being modified. arch/riscv/include/asm/tlbflush.h: 1. implement get_current_asid to get current program asid. 2. implement local_flush_tlb_asid to flush tlb with asid. Signed-off-by: Jiuyang Liu --- arch/riscv/include/asm/pgtable.h | 27 +++++++++++++++++++++++++++ arch/riscv/include/asm/tlbflush.h | 12 ++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index ebf817c1bdf4..5a47c60372c1 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -222,6 +222,16 @@ static inline int pte_write(pte_t pte) return pte_val(pte) & _PAGE_WRITE; } =20 +static inline int pte_user(pte_t pte) +{ + return pte_val(pte) & _PAGE_USER; +} + +static inline int pte_global(pte_t pte) +{ + return pte_val(pte) & _PAGE_GLOBAL; +} + static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; @@ -248,6 +258,11 @@ static inline int pte_special(pte_t pte) return pte_val(pte) & _PAGE_SPECIAL; } =20 +static inline int pte_leaf(pte_t pte) +{ + return pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC); +} + /* static inline pte_t pte_rdprotect(pte_t pte) */ =20 static inline pte_t pte_wrprotect(pte_t pte) @@ -358,6 +373,18 @@ static inline void set_pte_at(struct mm_struct *mm, flush_icache_pte(pteval); =20 set_pte(ptep, pteval); + + if (pte_present(pteval)) { + if (pte_leaf(pteval)) { + local_flush_tlb_page(addr); + } else { + if (pte_global(pteval)) + local_flush_tlb_all(); + else + local_flush_tlb_asid(); + + } + } } =20 static inline void pte_clear(struct mm_struct *mm, diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlb= flush.h index 394cfbccdcd9..1f9b62b3670b 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -21,6 +21,18 @@ static inline void local_flush_tlb_page(unsigned long ad= dr) { __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); } + +static inline unsigned long get_current_asid(void) +{ + return (csr_read(CSR_SATP) >> SATP_ASID_SHIFT) & SATP_ASID_MASK; +} + +static inline void local_flush_tlb_asid(void) +{ + unsigned long asid =3D get_current_asid(); + __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) : "memory"); +} + #else /* CONFIG_MMU */ #define local_flush_tlb_all() do { } while (0) #define local_flush_tlb_page(addr) do { } while (0) --=20 2.30.2