From nobody Tue Feb 10 14:49:53 2026 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=quarantine dis=quarantine) header.from=ti.com ARC-Seal: i=1; a=rsa-sha256; t=1616125548; cv=none; d=zohomail.com; s=zohoarc; b=WWhjGs/ehj7f4Q9uRgQgMwEFMk9aEdocJNY4XsnfgmollruoV3UwHIXTTHe5tjTIvi4yC72efuC0+Fm2hZjYwHyLFnIHJeE/OGrCWg/rP3GYkhv69JJx0S6CVef7e4TyouT1hzf+F5VhPv3opokwSDzQUH+BZ9OiYB172uJQjlE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616125548; h=Content-Type:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=0DjpT9RI6xBuiH/kvkStqjxXlo0KDPnEnU4C0SyCtBo=; b=FaXEOK/pomv5i3JraEgvABX8Jthclb5LothEcsOIfYW6NHthcBihy+RelS2otpXRNI5TQODVcds5YqjDcWs9HwkMbOq82bcnCup2lUPRsxXbhbwNO01+qnomjtf+fSQPXrhpzuvPpCpD4gmvOvCaFo//gjd+AR6claFq20PZXGo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=quarantine dis=quarantine) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1616125548018430.7223204907125; Thu, 18 Mar 2021 20:45:48 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233533AbhCSDpJ (ORCPT ); Thu, 18 Mar 2021 23:45:09 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:37372 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229948AbhCSDog (ORCPT ); Thu, 18 Mar 2021 23:44:36 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12J3iWjY040116; Thu, 18 Mar 2021 22:44:32 -0500 Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12J3iWKF125800 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 18 Mar 2021 22:44:32 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 18 Mar 2021 22:44:32 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Thu, 18 Mar 2021 22:44:31 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12J3iN0K039408; Thu, 18 Mar 2021 22:44:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1616125472; bh=0DjpT9RI6xBuiH/kvkStqjxXlo0KDPnEnU4C0SyCtBo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xKIMBwLxtB0YbbrdS74Ga3raII3wVAY/7Cu+Bva96XeIe/or/gnKljwOaKRtk30k2 DhOikcMo5DFXOTZmRE5jUl8K5BnS1SwTHfcch0y3BQag7AODHbACBVI7dVOKKJmwHp x0ZhZp7/RFDwKH9FypCPwCucK2SGoiMheinEb+9w= From: Aswath Govindraju CC: Vignesh Raghavendra , Lokesh Vutla , Kishon Vijay Abraham I , Aswath Govindraju , Faiz Abbas , Sekhar Nori , Nishanth Menon , Tero Kristo , Rob Herring , , , Subject: [PATCH v6 1/3] arm64: dts: ti: k3-j7200: Add gpio nodes Date: Fri, 19 Mar 2021 09:14:19 +0530 Message-ID: <20210319034422.17630-2-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210319034422.17630-1-a-govindraju@ti.com> References: <20210319034422.17630-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Faiz Abbas There are 4 instances of gpio modules in main domain: gpio0, gpio2, gpio4 and gpio6 Groups are created to provide protection between different processor virtual worlds. Each of these modules I/O pins are muxed within the group. Exactly one module can be selected to control the corresponding pin by selecting it in the pad mux configuration registers. This group in main domain pins out 69 lines (5 banks). Add DT modes for each module instance in the main domain. Similar to the gpio groups in main domain, there is one gpio group in wakeup domain with 2 module instances in it. The gpio group pins out 72 pins (6 banks) of the first 85 gpio lines. Add DT nodes for each module instance in the wakeup domain. Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori Signed-off-by: Aswath Govindraju Reviewed-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 72 +++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 34 +++++++++ 2 files changed, 106 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 17477ab0fd8e..e60650a62b14 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -672,6 +672,78 @@ }; }; =20 + main_gpio0: gpio@600000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <145>, <146>, <147>, <148>, + <149>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <69>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 105 0>; + clock-names =3D "gpio"; + }; + + main_gpio2: gpio@610000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <154>, <155>, <156>, <157>, + <158>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <69>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 107 0>; + clock-names =3D "gpio"; + }; + + main_gpio4: gpio@620000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00620000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <163>, <164>, <165>, <166>, + <167>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <69>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 109 0>; + clock-names =3D "gpio"; + }; + + main_gpio6: gpio@630000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00630000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <172>, <173>, <174>, <175>, + <176>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <69>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 111 0>; + clock-names =3D "gpio"; + }; + main_r5fss0: r5fss@5c00000 { compatible =3D "ti,j7200-r5fss"; ti,cluster-mode =3D <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 359e3e8a8cd0..1dd5b30edc6c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -107,6 +107,40 @@ ti,interrupt-ranges =3D <16 960 16>; }; =20 + wkup_gpio0: gpio@42110000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x42110000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&wkup_gpio_intr>; + interrupts =3D <103>, <104>, <105>, <106>, <107>, <108>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <85>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 113 0>; + clock-names =3D "gpio"; + }; + + wkup_gpio1: gpio@42100000 { + compatible =3D "ti,j721e-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x42100000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&wkup_gpio_intr>; + interrupts =3D <112>, <113>, <114>, <115>, <116>, <117>; + interrupt-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + ti,ngpio =3D <85>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 114 0>; + clock-names =3D "gpio"; + }; + mcu_navss: bus@28380000 { compatible =3D "simple-mfd"; #address-cells =3D <2>; --=20 2.17.1 From nobody Tue Feb 10 14:49:53 2026 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=quarantine dis=quarantine) header.from=ti.com ARC-Seal: i=1; a=rsa-sha256; t=1616125548; cv=none; d=zohomail.com; s=zohoarc; b=h9HDOlbVKtOiztMPbYaYg5ZFGVCQZZqU4kFcWvITQ5RrsPttw2G4+/HPVBBsU0Bur/GoTkh/lyh/CGJfMh9m//C27cRPjoiJrfGp6vZx/OJS2htDJzDs0r5EuwZX3umu04aLi5xe1rBgcKqNU+u+3otnKDzR9gy052osFcSDXXE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616125548; h=Content-Type:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; 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charset="utf-8" From: Faiz Abbas There are 6 gpio instances inside SoC with 2 groups as show below: Group one: wkup_gpio0, wkup_gpio1 Group two: main_gpio0, main_gpio2, main_gpio4, main_gpio6 Only one instance from each group can be used at a time. So use main_gpio0 and wkup_gpio0 in current linux context and disable the rest of the nodes. Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori Signed-off-by: Aswath Govindraju Reviewed-by: Grygorii Strashko --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 4a7182abccf5..b493f939b09a 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -122,6 +122,22 @@ status =3D "disabled"; }; =20 +&main_gpio2 { + status =3D "disabled"; +}; + +&main_gpio4 { + status =3D "disabled"; +}; + +&main_gpio6 { + status =3D "disabled"; +}; + +&wkup_gpio1 { + status =3D "disabled"; +}; + &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; --=20 2.17.1 From nobody Tue Feb 10 14:49:53 2026 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; 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Thu, 18 Mar 2021 22:44:41 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 18 Mar 2021 22:44:41 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Thu, 18 Mar 2021 22:44:41 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12J3iN0M039408; Thu, 18 Mar 2021 22:44:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1616125481; bh=Z1O6OM4HY7EczwZ488q9VaTYI4LeC5PWqK/HuDdcX2o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vsntlY+GzF15JGjO/EloQY2stZ+H8n1PtOK0LKFO4lv0cG+sbtWaLMdx1RpDZ6C0q rsLf2D1S1uUeIT4tvAaOugqyqPp4m5fVYK8ARfpN+1s1Sqp6L26gvpTL4aryDATh/a lBShB3M0Wz03ePnrw4irry/Ws8uxZRBEREaopil8= From: Aswath Govindraju CC: Vignesh Raghavendra , Lokesh Vutla , Kishon Vijay Abraham I , Aswath Govindraju , Nishanth Menon , Tero Kristo , Rob Herring , , , Subject: [PATCH v6 3/3] arm64: dts: ti: k3-j7200: Add support for higher speed modes and update delay select values for MMCSD subsystems Date: Fri, 19 Mar 2021 09:14:21 +0530 Message-ID: <20210319034422.17630-4-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210319034422.17630-1-a-govindraju@ti.com> References: <20210319034422.17630-1-a-govindraju@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) The following speed modes are now supported in J7200 SoC, - HS200 and HS400 modes at 1.8 V card voltage, in MMCSD0 subsystem [1]. - UHS-I speed modes in MMCSD1 subsystem [1]. Add support for UHS-I modes by adding voltage regulator device tree nodes and corresponding pinmux details, to power cycle and voltage switch cards. Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1 device tree nodes. Also update the delay values for various speed modes supported, based on the revised january 2021 J7200 datasheet[2]. [1] - section 12.3.6.1.1 MMCSD Features, in https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf, (SPRUIU1A =E2=80=93 JULY 2020 =E2=80=93 REVISED JANUARY 2021) [2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf, (SPRSP57B =E2=80=93 APRIL 2020 =E2=80=93 REVISED JANUARY 2021) Signed-off-by: Aswath Govindraju --- .../dts/ti/k3-j7200-common-proc-board.dts | 42 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 14 ++++++- 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index b493f939b09a..6f90c3b1cf45 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -16,6 +16,29 @@ stdout-path =3D "serial2:115200n8"; bootargs =3D "console=3DttyS2,115200n8 earlycon=3Dns16550a,mmio32,0x0280= 0000"; }; + + vdd_mmc1: fixedregulator-sd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpios =3D <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: gpio-regulator-vdd-sd-dv { + compatible =3D "regulator-gpio"; + regulator-name =3D "vdd_sd_dv"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vdd_sd_dv_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + gpios =3D <&main_gpio0 55 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0 + 3300000 0x1>; + }; }; =20 &wkup_pmx0 { @@ -45,6 +68,13 @@ }; =20 &main_pmx0 { + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ + J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins =3D < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_S= CL */ @@ -70,6 +100,12 @@ J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; }; + + vdd_sd_dv_pins_default: vdd_sd_dv_pins_default { + pinctrl-single,pins =3D < + J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ + >; + }; }; =20 &wkup_uart0 { @@ -157,6 +193,10 @@ }; =20 &main_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c0_pins_default>; + clock-frequency =3D <400000>; + exp1: gpio@20 { compatible =3D "ti,tca6416"; reg =3D <0x20>; @@ -206,6 +246,8 @@ /* SD card */ pinctrl-0 =3D <&main_mmc1_pins_default>; pinctrl-names =3D "default"; + vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vdd_sd_dv>; ti,driver-strength-ohm =3D <50>; disable-wp; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index e60650a62b14..f86c493a44f1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -512,11 +512,16 @@ ti,otap-del-sel-mmc-hs =3D <0x0>; ti,otap-del-sel-ddr52 =3D <0x6>; ti,otap-del-sel-hs200 =3D <0x8>; - ti,otap-del-sel-hs400 =3D <0x0>; + ti,otap-del-sel-hs400 =3D <0x5>; + ti,itap-del-sel-legacy =3D <0x10>; + ti,itap-del-sel-mmc-hs =3D <0xa>; ti,strobe-sel =3D <0x77>; + ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; bus-width =3D <8>; mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; dma-coherent; }; =20 @@ -534,7 +539,12 @@ ti,otap-del-sel-sdr50 =3D <0xc>; ti,otap-del-sel-sdr104 =3D <0x5>; ti,otap-del-sel-ddr50 =3D <0xc>; - no-1-8-v; + ti,itap-del-sel-legacy =3D <0x0>; + ti,itap-del-sel-sd-hs =3D <0x0>; + ti,itap-del-sel-sdr12 =3D <0x0>; + ti,itap-del-sel-sdr25 =3D <0x0>; + ti,clkbuf-sel =3D <0x7>; + ti,trm-icp =3D <0x8>; dma-coherent; }; =20 --=20 2.17.1