From nobody Tue Feb 10 19:34:21 2026 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=quarantine dis=quarantine) header.from=ti.com ARC-Seal: i=1; a=rsa-sha256; t=1616131254; cv=none; d=zohomail.com; s=zohoarc; b=QTSUqTecw27WB1gnkmEuOqtMW91AOS0kcGyT3GSbVLNYtFQX+wVMGX5cNFSQ8xLl4UFKVSBQ0h+6ROPBEiHKAGk3+efa1X60spZCBssr3SW9rd06rtoIhDkLwNAtVViPHw4Mecy2cFe2lPGcMcvoR0wh7eeSfnJFLfDTCpu9YBE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616131254; h=Content-Type:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=NJcx+bkr3QUnRA7nhTjRkkGYKzPKzmFbhQmfkIOo9Sc=; b=IDAJFkxdv/yvLZlZ64YRxJnKc1zxN3Bh2HrPqe8Rx+PaFJmzfKSL1Dbmxx5dZPsh1RCUrKab5MrikdrGGZS9aC5lFM6tn89O02wjBiolVUI8O/YkzvNZA1Da93FKrlfx1+vmNmz4MUCDzU7ZrA8sPyAM8BZ0W3K6cbflrBIIxuM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=quarantine dis=quarantine) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1616131254700798.4515543371243; Thu, 18 Mar 2021 22:20:54 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233828AbhCSFUQ (ORCPT ); Fri, 19 Mar 2021 01:20:16 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:59752 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231787AbhCSFUG (ORCPT ); Fri, 19 Mar 2021 01:20:06 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12J5K0n8074882; Fri, 19 Mar 2021 00:20:00 -0500 Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12J5K0UZ043814 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 19 Mar 2021 00:20:00 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 19 Mar 2021 00:20:00 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Fri, 19 Mar 2021 00:20:00 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12J5JqE1079026; Fri, 19 Mar 2021 00:19:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1616131200; bh=NJcx+bkr3QUnRA7nhTjRkkGYKzPKzmFbhQmfkIOo9Sc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hGIbuk5yOOppCK7eUN+jEAFQ+iqOFGVsLwoZl6bdJmbSNeP1/zJx9szuECVscz/EL sSvht+wj7S1Uh/00XT6JdjJz4NBl0bXXKXxbhDbSC4hnQZT8gjkbGEduXeuRffvwG/ +z0IA8BXlsq7hrPIsnOblHDstbvGiGsQpZA96/Cc= From: Aswath Govindraju CC: Vignesh Raghavendra , Lokesh Vutla , Grygorii Strashko , Aswath Govindraju , Nishanth Menon , Tero Kristo , Rob Herring , , , Subject: [PATCH v3 1/2] arm64: dts: ti: k3-am64: Add GPIO DT nodes Date: Fri, 19 Mar 2021 10:49:49 +0530 Message-ID: <20210319051950.17549-2-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210319051950.17549-1-a-govindraju@ti.com> References: <20210319051950.17549-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree nodes for GPIO modules and interrupt controller in main and mcu domains. Signed-off-by: Aswath Govindraju --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 45 ++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 27 ++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index a03b66456062..b997d13f9ec5 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -373,6 +373,51 @@ clocks =3D <&k3_clks 145 0>; }; =20 + main_gpio_intr: interrupt-controller0 { + compatible =3D "ti,sci-intr"; + ti,intr-trigger-type =3D <1>; + interrupt-controller; + interrupt-parent =3D <&gic500>; + #interrupt-cells =3D <1>; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <3>; + ti,interrupt-ranges =3D <0 32 16>; + }; + + main_gpio0: gpio@600000 { + compatible =3D "ti,am64-gpio", "ti,keystone-gpio"; + reg =3D <0x0 0x00600000 0x0 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells =3D <2>; + ti,ngpio =3D <87>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 77 0>; + clock-names =3D "gpio"; + }; + + main_gpio1: gpio@601000 { + compatible =3D "ti,am64-gpio", "ti,keystone-gpio"; + reg =3D <0x0 0x00601000 0x0 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio_intr>; + interrupts =3D <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells =3D <2>; + ti,ngpio =3D <88>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 78 0>; + clock-names =3D "gpio"; + }; + sdhci0: mmc@fa10000 { compatible =3D "ti,am64-sdhci-8bit"; reg =3D <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am64-mcu.dtsi index 1d2be485a669..99e94dee1bd4 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -73,4 +73,31 @@ power-domains =3D <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 148 0>; }; + + mcu_gpio_intr: interrupt-controller1 { + compatible =3D "ti,sci-intr"; + ti,intr-trigger-type =3D <1>; + interrupt-controller; + interrupt-parent =3D <&gic500>; + #interrupt-cells =3D <1>; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <5>; + ti,interrupt-ranges =3D <0 104 4>; + }; + + mcu_gpio0: gpio@4201000 { + compatible =3D "ti,am64-gpio", "keystone-gpio"; + reg =3D <0x0 0x4201000 0x0 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&mcu_gpio_intr>; + interrupts =3D <30>, <31>; + interrupt-controller; + #interrupt-cells =3D <2>; + ti,ngpio =3D <23>; + ti,davinci-gpio-unbanked =3D <0>; + power-domains =3D <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 79 0>; + clock-names =3D "gpio"; + }; }; --=20 2.17.1