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[2a01:cb00:8bd:2700:41a0:a0f4:308e:afc0]) by smtp.gmail.com with ESMTPSA id l14sm17173952wrm.77.2021.04.07.14.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 14:21:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mP+Vc0+rJsbzL9hsHa8A36fu38vw4kqpWBwZhYOxhTg=; b=RexRqRaA26YijY8LmnBbuW7KCplc8yGNRT7Y3PgP+x6oLQr0EX+Pjg/MCDhLTzZPSy iq9tPnGleVrYt4i95Bs5pGJa7TU14ZGKZWwcblg/OPOQD6QaWNma/yJfPJUyd46MGR8U co6gdszVtlFmY5FKSIiYLRsVkYr0W7RjkG4ja3MjDEtRiKWVAlH41j755PebOTYyGQmP mEUD8TEY1JUvX4JksEhTitpYIbp/0jQRus5HbZrEj9u26RsSeoBZQi6rATqrdJdLeAcu qLxVW7imUNVhiTzUjovEEmAZltlxrZ0lwsjPsju+t2LZhqTBJsLY0RZ4kLWH4FFa7uCU cMlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mP+Vc0+rJsbzL9hsHa8A36fu38vw4kqpWBwZhYOxhTg=; b=eCuDncVzGZ6YJhklK5o3iALGKCIzrsu+jRxAc9ANmNZVMLZGaNvABbie8wP02bzvop k1Oig8ab7AV64Ua2CUVPFth3eh+Jry/4FY1jFBraBQBA//fMaIjs4f1OzeUiXstAmCV5 l1JZNArwp/42J2Sh2uwPigpLI+FllYlU8tUV7AxZ+fadPn5VMqYLj1tLo+sLTN6D9/B+ yTy3rjHrouT6Umj7793Am3jCDxfzSGTf2Bbnll5L2HIUtfTEJLKFRIwOzRQdRHzja4iK Sd8VNg7+JAOoRE3yyajr7HkIjE4KHEIaf+989cVPT3YVfPhdomVbCJlTUVSXE2BG31UL oJ9w== X-Gm-Message-State: AOAM531KIR963ADgdvyMdAIIAv5irfNx58Fzy9mACb+a41brXJrJvoBW hU3RCfvOSrClU2kdis1PGwk= X-Google-Smtp-Source: ABdhPJzFvCLHif6HdG/+/FbfYRxVTDz6YWqnOsxzb25RExafgzamf7BRMgth1iJaJ/vXDZxny1FTew== X-Received: by 2002:adf:eb0a:: with SMTP id s10mr6771728wrn.6.1617830487708; Wed, 07 Apr 2021 14:21:27 -0700 (PDT) From: Adrien Grassein Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, l.stach@pengutronix.de, Anson.Huang@nxp.com, krzk@kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, qiangqing.zhang@nxp.com, alice.guo@nxp.com, aford173@gmail.com, agx@sigxcpu.org, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Adrien Grassein Subject: [PATCH v1 1/7] soc: imx: gpcv2: check for errors when r/w registers Date: Wed, 7 Apr 2021 23:21:16 +0200 Message-Id: <20210407212122.626137-2-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407212122.626137-1-adrien.grassein@gmail.com> References: <20210407212122.626137-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Errors were not checked after each access to registers and clocks initialisation. Signed-off-by: Adrien Grassein --- drivers/soc/imx/gpcv2.c | 62 ++++++++++++++++++++++++++++++----------- 1 file changed, 45 insertions(+), 17 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index db7e7fc321b1..8ec5b1b817c7 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -140,8 +140,12 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm= _domain *genpd, int i, ret =3D 0; u32 pxx_req; =20 - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, domain->bits.map); + ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, domain->bits.map); + if (ret) { + dev_err(domain->dev, "failed to map GPC PGC domain\n"); + return ret; + } =20 if (has_regulator && on) { ret =3D regulator_enable(domain->regulator); @@ -152,19 +156,39 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_p= m_domain *genpd, } =20 /* Enable reset clocks for all devices in the domain */ - for (i =3D 0; i < domain->num_clks; i++) - clk_prepare_enable(domain->clk[i]); + for (i =3D 0; i < domain->num_clks; i++) { + ret =3D clk_prepare_enable(domain->clk[i]); + if (ret) { + dev_err(domain->dev, "failed to enable clocks\n"); + goto disable_clocks; + } + } =20 - if (enable_power_control) - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + if (enable_power_control) { + ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + if (ret) { + dev_err(domain->dev, "failed to enable power control\n"); + goto disable_clocks; + } + } =20 - if (domain->bits.hsk) - regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, - domain->bits.hsk, on ? domain->bits.hsk : 0); + if (domain->bits.hsk) { + ret =3D regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, + domain->bits.hsk, + on ? domain->bits.hsk : 0); + if (ret) { + dev_err(domain->dev, "Failed to initiate handshake\n"); + goto disable_power_control; + } + } =20 - regmap_update_bits(domain->regmap, offset, - domain->bits.pxx, domain->bits.pxx); + ret =3D regmap_update_bits(domain->regmap, offset, + domain->bits.pxx, domain->bits.pxx); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto disable_power_control; + } =20 /* * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait @@ -173,8 +197,15 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm= _domain *genpd, ret =3D regmap_read_poll_timeout(domain->regmap, offset, pxx_req, !(pxx_req & domain->bits.pxx), 0, USEC_PER_MSEC); - if (ret) { + if (ret) dev_err(domain->dev, "failed to command PGC\n"); + +disable_power_control: + if (enable_power_control) + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR, 0); + + if (ret) { /* * If we were in a process of enabling a * domain and failed we might as well disable @@ -185,10 +216,7 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm= _domain *genpd, on =3D !on; } =20 - if (enable_power_control) - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, 0); - +disable_clocks: /* Disable reset clocks for all devices in the domain */ for (i =3D 0; i < domain->num_clks; i++) clk_disable_unprepare(domain->clk[i]); --=20 2.25.1 From nobody Thu May 2 19:03:59 2024 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1617830525; cv=none; d=zohomail.com; s=zohoarc; b=aG9pSSXFL35H36DzcN2sSJcqaCxawD1+EwYAa8jlhZeyeam4MncGC+Kw1l8ZnHSRg/nd6Tzm69TCfvW2lG5auUPnqHVu41b2KeYf4ZGl5l57vfpxlGw6tMgAvzJStmkjBn/6VU5xfS5W+Ix/LBs8S7pcD9QrDbgOmb7aGgxiYeo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617830525; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=LXmODUYJ5jVMVtm5p+B0QGH2Rwv1W+jbpwPjPTOXLtA=; b=kAZoGs1FsrDZ5KPbAdneq7XaM4De7nD/PpdidEhBzcGhc6cFZheE7IaXGicS5QNJGiuZmBiNZdPDVhNT59byPi1Y0np3qqNzEcqjcvWzpf0srGQHmgrlO8xtLmN4l+lGO/x49NyLsSH4UQuXHf7bjUBPqagyPqUk4N0N2rZA9kY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1617830525564460.6856473069138; Wed, 7 Apr 2021 14:22:05 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232623AbhDGVWO (ORCPT ); Wed, 7 Apr 2021 17:22:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232542AbhDGVVm (ORCPT ); Wed, 7 Apr 2021 17:21:42 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E06BC061763; Wed, 7 Apr 2021 14:21:30 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id a6so13424904wrw.8; Wed, 07 Apr 2021 14:21:30 -0700 (PDT) Received: from adgra-XPS-15-9570.home (2a01cb0008bd270041a0a0f4308eafc0.ipv6.abo.wanadoo.fr. [2a01:cb00:8bd:2700:41a0:a0f4:308e:afc0]) by smtp.gmail.com with ESMTPSA id l14sm17173952wrm.77.2021.04.07.14.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 14:21:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LXmODUYJ5jVMVtm5p+B0QGH2Rwv1W+jbpwPjPTOXLtA=; b=srlxUl/yqpRC8W+P/vxvbZStdaJ/ip7ir5D7+Qk45ij1lqalIkWv6auJB7HJvoaiRS gE/A5Q9HaOhaHrPJ82ac3G5Hh9Fz1ad11iI0txrfgjJnYKc8EhGY5sIlfV5HFl8FA84a VgVxapYnAOxz6X6sj5D7lHwnf/uQLIQhDmIgn/hg/3d0X5B2W7w4toqmA8eMA91a/XzQ A22YZHwNZadxiWonRDN+ruDWjomhaVziqLvRIwolgpRQWdKuI3c+g7GCLzcjrJiqUQ/h 3ahuM4X9nhy6KdWDZ1q+cK349yW5wqzxIKAARDafbXEgQvOro8sAmd2owZRj3ZHBFLZI eETg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LXmODUYJ5jVMVtm5p+B0QGH2Rwv1W+jbpwPjPTOXLtA=; b=t/UNmlfknuxv5CMINXBWsh035txkprBm1dAWuvPv2EhvhdbECgK3rYYXQmUzSFRujq Zl6sNj3HeW+x6O6dmY58mQp7depD9U9NY03iJyBLZ1y8O5H89eBTDyts6GPr33T30QCY HO18aoVyzB6yjVckaCsQ96NqV5c1J0VPUwMVQO1bg9NewaatxquiID8Ih0Dz6TKNIzA+ a2Y617FIcXbDTj4/yCvvSq7PXXe5xnSlvlZFuLKFA8g219MA+hvz/CdtfCGvsc0BoA3M 9V6X/C7JE6Qj12aU9tuUUFsftvRS0z7Rg6HJXE+cTffj/sdBE98d/7FKc712dN0xRWAV SWug== X-Gm-Message-State: AOAM530wkVsoffbduhnJJAfpyCdt3iMvK3Z3h936E7oqP72sHk8ZxrZ5 yNEvwA/ZRdg/kWOwkC9tlMI= X-Google-Smtp-Source: ABdhPJzX8VS/ZPUnUOkNbPvXBv/HrzJ5cSeCHa2JsriOePZlZXEPvqsFvO7Tt2DQI8H/3pd1P/3NIg== X-Received: by 2002:adf:e743:: with SMTP id c3mr3707043wrn.408.1617830488994; Wed, 07 Apr 2021 14:21:28 -0700 (PDT) From: Adrien Grassein Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, l.stach@pengutronix.de, Anson.Huang@nxp.com, krzk@kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, qiangqing.zhang@nxp.com, alice.guo@nxp.com, aford173@gmail.com, agx@sigxcpu.org, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Adrien Grassein Subject: [PATCH v1 2/7] soc: imx: gpcv2: Fix power up/down sequence Date: Wed, 7 Apr 2021 23:21:17 +0200 Message-Id: <20210407212122.626137-3-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407212122.626137-1-adrien.grassein@gmail.com> References: <20210407212122.626137-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Power up/down sequence were wrongly scheduled. The ADB400 were triggered at the bad time. The Handshake were not checked. The solution is to: - Split power up and power down sequences; - Add a register holding the bit to check; Signed-off-by: Adrien Grassein --- drivers/soc/imx/gpcv2.c | 235 ++++++++++++++++++++++++++++------------ 1 file changed, 163 insertions(+), 72 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 8ec5b1b817c7..7afb81489f21 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -70,8 +70,11 @@ #define GPC_PU_PWRHSK 0x1fc =20 #define IMX8M_GPU_HSK_PWRDNREQN BIT(6) +#define IMX8M_GPU_HSK_PWRDNACKN BIT(26) #define IMX8M_VPU_HSK_PWRDNREQN BIT(5) +#define IMX8M_VPU_HSK_PWRDNACKN BIT(25) #define IMX8M_DISP_HSK_PWRDNREQN BIT(4) +#define IMX8M_DISP_HSK_PWRDNACKN BIT(24) =20 /* * The PGC offset values in Reference Manual @@ -102,6 +105,8 @@ =20 #define GPC_CLK_MAX 6 =20 +static DEFINE_MUTEX(gpc_pd_mutex); + struct imx_pgc_domain { struct generic_pm_domain genpd; struct regmap *regmap; @@ -114,7 +119,8 @@ struct imx_pgc_domain { const struct { u32 pxx; u32 map; - u32 hsk; + u32 hsk_req; + u32 hsk_ack; } bits; =20 const int voltage; @@ -127,34 +133,25 @@ struct imx_pgc_domain_data { const struct regmap_access_table *reg_access_table; }; =20 -static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd, - bool on) +static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd) { struct imx_pgc_domain *domain =3D container_of(genpd, struct imx_pgc_domain, genpd); - unsigned int offset =3D on ? - GPC_PU_PGC_SW_PUP_REQ : GPC_PU_PGC_SW_PDN_REQ; - const bool enable_power_control =3D !on; - const bool has_regulator =3D !IS_ERR(domain->regulator); int i, ret =3D 0; - u32 pxx_req; + u32 value; =20 - ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, domain->bits.map); - if (ret) { - dev_err(domain->dev, "failed to map GPC PGC domain\n"); - return ret; - } - - if (has_regulator && on) { + /* Enable regulator if needed */ + if (!IS_ERR(domain->regulator)) { ret =3D regulator_enable(domain->regulator); if (ret) { dev_err(domain->dev, "failed to enable regulator\n"); - goto unmap; + return ret; } } =20 + mutex_lock(&gpc_pd_mutex); + /* Enable reset clocks for all devices in the domain */ for (i =3D 0; i < domain->num_clks; i++) { ret =3D clk_prepare_enable(domain->clk[i]); @@ -164,87 +161,178 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_= pm_domain *genpd, } } =20 - if (enable_power_control) { - ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + /* Map the domain to the A53 core */ + ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, domain->bits.map); + if (ret) { + dev_err(domain->dev, "failed to map GPC PGC domain\n"); + goto disable_clocks; + } + + /* Request Power Up of the domain */ + ret =3D regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, + domain->bits.pxx, domain->bits.pxx); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto unmap; + } + + /* + * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait + * for PUP_REQ/PDN_REQ bit to be cleared + */ + ret =3D regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, + value, + !(value & domain->bits.pxx), + 0, USEC_PER_MSEC); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto unmap; + } + + /* Disable power control */ + ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR, 0); + if (ret) { + dev_err(domain->dev, "Failed to disable power control !\n"); + goto unmap; + } + + /* request the ADB400 to power up */ + if (domain->bits.hsk_req) { + regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, + domain->bits.hsk_req, domain->bits.hsk_req); + + ret =3D regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, + value, + (value & domain->bits.hsk_ack), + 0, USEC_PER_MSEC); + if (ret) + dev_err(domain->dev, "Bad ACK while powering on %s\n", + genpd->name); + } + + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); + + /* Disable all clocks */ + for (i =3D 0; i < domain->num_clks; i++) + clk_disable_unprepare(domain->clk[i]); + + mutex_unlock(&gpc_pd_mutex); + + return 0; + +unmap: + if (domain->bits.map) + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); + +disable_clocks: + for (i--; i >=3D 0; i--) + clk_disable_unprepare(domain->clk[i]); + + mutex_unlock(&gpc_pd_mutex); + return ret; +} + +static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd) +{ + struct imx_pgc_domain *domain =3D container_of(genpd, + struct imx_pgc_domain, + genpd); + int i, ret =3D 0; + u32 value; + + mutex_lock(&gpc_pd_mutex); + + /* Enable reset clocks for all devices in the domain */ + for (i =3D 0; i < domain->num_clks; i++) { + ret =3D clk_prepare_enable(domain->clk[i]); if (ret) { - dev_err(domain->dev, "failed to enable power control\n"); + dev_err(domain->dev, "failed to enable clocks\n"); goto disable_clocks; } } =20 - if (domain->bits.hsk) { - ret =3D regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, - domain->bits.hsk, - on ? domain->bits.hsk : 0); - if (ret) { - dev_err(domain->dev, "Failed to initiate handshake\n"); - goto disable_power_control; - } + /* Map the domain to the A53 core */ + ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, domain->bits.map); + if (ret) { + dev_err(domain->dev, "failed to map GPC PGC domain\n"); + goto disable_clocks; + } + + /* request the ADB400 to power down */ + if (domain->bits.hsk_req) { + regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, + domain->bits.hsk_req, 0); + + ret =3D regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, + value, + !(value & domain->bits.hsk_ack), + 0, USEC_PER_MSEC); + if (ret) + dev_err(domain->dev, "Bad ACK while powering down %s\n", + genpd->name); + } =20 - ret =3D regmap_update_bits(domain->regmap, offset, + /* Enable power control */ + ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + if (ret) { + dev_err(domain->dev, "Failed to enable power control !\n"); + goto unmap; + } + + /* Request Power Down of the domain */ + ret =3D regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, domain->bits.pxx, domain->bits.pxx); if (ret) { dev_err(domain->dev, "failed to command PGC\n"); - goto disable_power_control; + goto unmap; } =20 /* * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait * for PUP_REQ/PDN_REQ bit to be cleared */ - ret =3D regmap_read_poll_timeout(domain->regmap, offset, pxx_req, - !(pxx_req & domain->bits.pxx), + ret =3D regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, + value, + !(value & domain->bits.pxx), 0, USEC_PER_MSEC); if (ret) dev_err(domain->dev, "failed to command PGC\n"); =20 -disable_power_control: - if (enable_power_control) - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, 0); - - if (ret) { - /* - * If we were in a process of enabling a - * domain and failed we might as well disable - * the regulator we just enabled. And if it - * was the opposite situation and we failed to - * power down -- keep the regulator on - */ - on =3D !on; + if (!IS_ERR(domain->regulator)) { + ret =3D regulator_disable(domain->regulator); + if (ret) + dev_err(domain->dev, "failed to disable regulator\n"); } =20 -disable_clocks: - /* Disable reset clocks for all devices in the domain */ + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); + + /* Disable all clocks */ for (i =3D 0; i < domain->num_clks; i++) clk_disable_unprepare(domain->clk[i]); =20 - if (has_regulator && !on) { - int err; + mutex_unlock(&gpc_pd_mutex); + return 0; =20 - err =3D regulator_disable(domain->regulator); - if (err) - dev_err(domain->dev, - "failed to disable regulator: %d\n", err); - /* Preserve earlier error code */ - ret =3D ret ?: err; - } unmap: - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, 0); - return ret; -} + if (domain->bits.map) + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); =20 -static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd) -{ - return imx_gpc_pu_pgc_sw_pxx_req(genpd, true); -} +disable_clocks: + for (i--; i >=3D 0; i--) + clk_disable_unprepare(domain->clk[i]); + + mutex_unlock(&gpc_pd_mutex); + return ret; =20 -static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd) -{ - return imx_gpc_pu_pgc_sw_pxx_req(genpd, false); } =20 static const struct imx_pgc_domain imx7_pgc_domains[] =3D { @@ -370,7 +458,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = =3D { .bits =3D { .pxx =3D IMX8M_GPU_SW_Pxx_REQ, .map =3D IMX8M_GPU_A53_DOMAIN, - .hsk =3D IMX8M_GPU_HSK_PWRDNREQN, + .hsk_req =3D IMX8M_GPU_HSK_PWRDNREQN, + .hsk_ack =3D IMX8M_GPU_HSK_PWRDNACKN }, .pgc =3D IMX8M_PGC_GPU, }, @@ -382,7 +471,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = =3D { .bits =3D { .pxx =3D IMX8M_VPU_SW_Pxx_REQ, .map =3D IMX8M_VPU_A53_DOMAIN, - .hsk =3D IMX8M_VPU_HSK_PWRDNREQN, + .hsk_req =3D IMX8M_VPU_HSK_PWRDNREQN, + .hsk_ack =3D IMX8M_VPU_HSK_PWRDNACKN }, .pgc =3D IMX8M_PGC_VPU, }, @@ -394,7 +484,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = =3D { .bits =3D { .pxx =3D IMX8M_DISP_SW_Pxx_REQ, .map =3D IMX8M_DISP_A53_DOMAIN, - .hsk =3D IMX8M_DISP_HSK_PWRDNREQN, + .hsk_req =3D IMX8M_DISP_HSK_PWRDNREQN, + .hsk_ack =3D IMX8M_DISP_HSK_PWRDNACKN }, .pgc =3D IMX8M_PGC_DISP, }, --=20 2.25.1 From nobody Thu May 2 19:03:59 2024 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1617830532; cv=none; d=zohomail.com; s=zohoarc; b=mE2oW4XazNivWIq/WmWQ5ZT9brFnFJE1fROuPC2F7cFqRDopuU7LT2meQ3XSmhZR9GKKQSOAa7nkdeUj1Fv7LqQ8efokPErYIZRaJDpEAsJSmm+eGq5Vx1bfi9d55mW7SmcGixHabE+yC8uveRjfR4MobPMSp6901lV4uNRJgbc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617830532; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=l8ngQ/qQ8Weuy1yqO9HG4J00ciWdsd3MWP0cjimJPkc=; b=HzQqYr4dvuwHBS60Gp3lzwuy6odHP3TAnOKrIAgWGulo5y+N7mmHioxhxy/0cFFZJlFJnvLIvxGVSyM7rbDoAlnfwzknIyUUBHr3oXDxgBUBuXBDnmf6gU4BxRWroouAk5nSKstYIiIn9kPxJ4RgAEZbhqfZdQfYTi/uiPzGIXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1617830532712501.25245285445453; Wed, 7 Apr 2021 14:22:12 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232760AbhDGVWV (ORCPT ); Wed, 7 Apr 2021 17:22:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232563AbhDGVVr (ORCPT ); Wed, 7 Apr 2021 17:21:47 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 550D1C061765; Wed, 7 Apr 2021 14:21:31 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id x15so10231782wrq.3; Wed, 07 Apr 2021 14:21:31 -0700 (PDT) Received: from adgra-XPS-15-9570.home (2a01cb0008bd270041a0a0f4308eafc0.ipv6.abo.wanadoo.fr. [2a01:cb00:8bd:2700:41a0:a0f4:308e:afc0]) by smtp.gmail.com with ESMTPSA id l14sm17173952wrm.77.2021.04.07.14.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 14:21:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l8ngQ/qQ8Weuy1yqO9HG4J00ciWdsd3MWP0cjimJPkc=; b=C3TCxPmUYVy4U/tF+I1Fh1OLG9wqPm7A1ArCrx1ZYzrt5UD5EyH4HBFZYvK7c7ysCI WKFvndVJdYI+3cxIq5HCFvSIVYH3n9G1gBoH7NGfICw2EWjKAziVojOGn0XCu8nsAY/I OtBCa7LhS7VkGaborgVexzPWO8KHF+3Fkik+JhGhxsFS+rog7BswM87k6Cfskm25qgqJ kGGv5lpDzNM4mqs4GwuG0MWkXABAfyd8s7/TC4zpVOQaGMFMRJq5JSjLJQhN6MCdF1P8 BMbluiGbuWxzX3Zxq5j6vl2IMkfYQZ5g4U9BOcyWa/8B5JPmBYx/Ru72GAQJZg9w4ilX IIDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l8ngQ/qQ8Weuy1yqO9HG4J00ciWdsd3MWP0cjimJPkc=; b=g+FgfBFMNvODhnUmTNfXbgvS8yxWn+dfX/ah+Fp3Rmk+HQl5Bq+n4iSs5qh3Xjt48d 24cnDu9F7r677kR+hna+RbpCXDij3G4GqaCV8aLFLBvP9o/eh7m0hJeWeenPPXNscQFB jzOij0iUncjZVz6TI1Qv4BtIozDpl2I4+AqDb/EhrkDRWoB9n5uKeXD03SdP4T9YBH6j QlXFwB23M9YwkvGLor1/BIHyHo/EPDqH+12GXc1HXIYQYi0ZEnYxJM0buz7fG4AYzPDo MuIlq8X8lJ686q6+OG8GiAT19P34Fp9J6zX6AGWrlJsenZYEuy3bIh3Qg4mC8cbJEU4G QZRw== X-Gm-Message-State: AOAM531n+9TOWYNaBpAdL/ma837QBHRxcP/RlvnBzeYGgKEsPI2gxni3 SktmM3CQn7Q8XjpyfqeneTrQ5f2Hk1jkdQ== X-Google-Smtp-Source: ABdhPJwV/H7G5Ylw18MK4ozOBB5I4Gcl1khWcTYtonjBlD7+FhLtLorNaNriv3LLEGhhSbE7PznZMQ== X-Received: by 2002:adf:cd04:: with SMTP id w4mr6737511wrm.148.1617830489880; Wed, 07 Apr 2021 14:21:29 -0700 (PDT) From: Adrien Grassein Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, l.stach@pengutronix.de, Anson.Huang@nxp.com, krzk@kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, qiangqing.zhang@nxp.com, alice.guo@nxp.com, aford173@gmail.com, agx@sigxcpu.org, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Adrien Grassein Subject: [PATCH v1 3/7] soc: imx: gpcv2: allow domains without power sequence control Date: Wed, 7 Apr 2021 23:21:18 +0200 Message-Id: <20210407212122.626137-4-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407212122.626137-1-adrien.grassein@gmail.com> References: <20210407212122.626137-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" On new SOCs, some domains does not have power sequence control registers. Signed-off-by: Adrien Grassein --- drivers/soc/imx/gpcv2.c | 134 +++++++++++++++++++++------------------- 1 file changed, 72 insertions(+), 62 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 7afb81489f21..d97a53502753 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -162,40 +162,44 @@ static int imx_gpc_pu_pgc_sw_pup_req(struct generic_p= m_domain *genpd) } =20 /* Map the domain to the A53 core */ - ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, domain->bits.map); - if (ret) { - dev_err(domain->dev, "failed to map GPC PGC domain\n"); - goto disable_clocks; + if (domain->bits.map) { + ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, domain->bits.map); + if (ret) { + dev_err(domain->dev, "failed to map GPC PGC domain\n"); + goto disable_clocks; + } } =20 /* Request Power Up of the domain */ - ret =3D regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, - domain->bits.pxx, domain->bits.pxx); - if (ret) { - dev_err(domain->dev, "failed to command PGC\n"); - goto unmap; - } + if (domain->bits.pxx) { + ret =3D regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, + domain->bits.pxx, domain->bits.pxx); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto unmap; + } =20 - /* - * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait - * for PUP_REQ/PDN_REQ bit to be cleared - */ - ret =3D regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, - value, - !(value & domain->bits.pxx), - 0, USEC_PER_MSEC); - if (ret) { - dev_err(domain->dev, "failed to command PGC\n"); - goto unmap; - } + /* + * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait + * for PUP_REQ/PDN_REQ bit to be cleared + */ + ret =3D regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, + value, + !(value & domain->bits.pxx), + 0, USEC_PER_MSEC); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto unmap; + } =20 - /* Disable power control */ - ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, 0); - if (ret) { - dev_err(domain->dev, "Failed to disable power control !\n"); - goto unmap; + /* Disable power control */ + ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR, 0); + if (ret) { + dev_err(domain->dev, "Failed to disable power control !\n"); + goto unmap; + } } =20 /* request the ADB400 to power up */ @@ -212,8 +216,9 @@ static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_= domain *genpd) genpd->name); } =20 - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, 0); + if (domain->bits.map) + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); =20 /* Disable all clocks */ for (i =3D 0; i < domain->num_clks; i++) @@ -256,11 +261,13 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_p= m_domain *genpd) } =20 /* Map the domain to the A53 core */ - ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, domain->bits.map); - if (ret) { - dev_err(domain->dev, "failed to map GPC PGC domain\n"); - goto disable_clocks; + if (domain->bits.map) { + ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, domain->bits.map); + if (ret) { + dev_err(domain->dev, "failed to map GPC PGC domain\n"); + goto disable_clocks; + } } =20 /* request the ADB400 to power down */ @@ -278,32 +285,34 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_p= m_domain *genpd) =20 } =20 - /* Enable power control */ - ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); - if (ret) { - dev_err(domain->dev, "Failed to enable power control !\n"); - goto unmap; - } + if (domain->bits.pxx) { + /* Enable power control */ + ret =3D regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + if (ret) { + dev_err(domain->dev, "Failed to enable power control !\n"); + goto unmap; + } =20 - /* Request Power Down of the domain */ - ret =3D regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, - domain->bits.pxx, domain->bits.pxx); - if (ret) { - dev_err(domain->dev, "failed to command PGC\n"); - goto unmap; - } + /* Request Power Down of the domain */ + ret =3D regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, + domain->bits.pxx, domain->bits.pxx); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto unmap; + } =20 - /* - * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait - * for PUP_REQ/PDN_REQ bit to be cleared - */ - ret =3D regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, - value, - !(value & domain->bits.pxx), - 0, USEC_PER_MSEC); - if (ret) - dev_err(domain->dev, "failed to command PGC\n"); + /* + * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait + * for PUP_REQ/PDN_REQ bit to be cleared + */ + ret =3D regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, + value, + !(value & domain->bits.pxx), + 0, USEC_PER_MSEC); + if (ret) + dev_err(domain->dev, "failed to command PGC\n"); + } =20 if (!IS_ERR(domain->regulator)) { ret =3D regulator_disable(domain->regulator); @@ -311,8 +320,9 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_= domain *genpd) dev_err(domain->dev, "failed to disable regulator\n"); } =20 - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, 0); + if (domain->bits.map) + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); =20 /* Disable all clocks */ for (i =3D 0; i < domain->num_clks; i++) --=20 2.25.1 From nobody Thu May 2 19:03:59 2024 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1617830530; cv=none; d=zohomail.com; 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[2a01:cb00:8bd:2700:41a0:a0f4:308e:afc0]) by smtp.gmail.com with ESMTPSA id l14sm17173952wrm.77.2021.04.07.14.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 14:21:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=C+Sv7ebyhZdmYr8zuNmK8przgQqiTzBeblvn6JjaT24=; b=XKD8B7qsQuuWd1cNL5YOrIfkh/B80SxKacpgd/mGcX8L7wxF5vEB6F3IZKHOJZ+tSi VgxkXjROxu8DOyLlyfrsjSXCk8XuS12BOqOJRtaP0M1S4kwlJYskhOH2zkAwoyy8xtx7 cQEcpzBok0YoUup3YateFoVWofliJr13HcV7TPH1fS/sEredskpOhrqGzCMqssc5t6JW aGSizURYMPrnBzP/30BAT/UpdJvsT8wHsAMkHHiw4y1tP2knBZd1/0pbzz02wEqlsp6o oIeajgMDgofsI/9yD2UrnbS/F4HGUGAANXYqCbQ55+zVtFk/I4zPQzSmlcZf0+C+YJuu XEAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C+Sv7ebyhZdmYr8zuNmK8przgQqiTzBeblvn6JjaT24=; b=I0ndKaHXPEVHYaFRrjlr8h1U8kL6fsnq3gFc2HK7G1oq0EX0RkxVrqIv4K4OAGqJDT WuY/GIzdP5gsJsJoIfWTH62i0dzK62K2/hd2qClxe1gnbyB8YvYBDiVz9mciqz6lZjSf 9RE+5SNf+9qkDj03h867hZ9TYefJiBroF7L3AEUkS+5T2ojz0ldNfZWvfeQjS9VX+DRv AKR/lhR9NHX4wcdKHkTOLwDkOdHizwhnIb3qzQ9fEVd6AbCWODEqA6fHGZC0br6HY06c fJvrfBjQ6g6Q4KO0RpbY+TcNU0T+qsFQeU6AP0XzumZaZhpMN4tgIqP0j0HTBlEt5U+2 GxLg== X-Gm-Message-State: AOAM533CH5bZZ2OrMLJgzLbp/8w2No5AHxZHIkmMirY5f674IKkp7mxO 6gArTIiFc3BH7zaHBmsUIPM= X-Google-Smtp-Source: ABdhPJzEcI7EbB2e2oDATbJrtla4jwk4IkNB5X15tDJWQzL9U1sVz37qdbX+D8tXFi4fuBGD9a6Ojw== X-Received: by 2002:a1c:6a13:: with SMTP id f19mr2241444wmc.145.1617830490525; Wed, 07 Apr 2021 14:21:30 -0700 (PDT) From: Adrien Grassein Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, l.stach@pengutronix.de, Anson.Huang@nxp.com, krzk@kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, qiangqing.zhang@nxp.com, alice.guo@nxp.com, aford173@gmail.com, agx@sigxcpu.org, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Adrien Grassein Subject: [PATCH v1 4/7] dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM Date: Wed, 7 Apr 2021 23:21:19 +0200 Message-Id: <20210407212122.626137-5-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407212122.626137-1-adrien.grassein@gmail.com> References: <20210407212122.626137-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Update documentation for i.MX8MM. Signed-off-by: Adrien Grassein --- .../bindings/power/fsl,imx-gpcv2.yaml | 7 +++++-- include/dt-bindings/power/imx8mm-power.h | 21 +++++++++++++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/power/imx8mm-power.h diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/D= ocumentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index a96e6dbf1858..04928a173698 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -26,6 +26,7 @@ properties: enum: - fsl,imx7d-gpc - fsl,imx8mq-gpc + - fsl,imx8mm-pgc =20 reg: maxItems: 1 @@ -52,8 +53,10 @@ properties: reg: description: | Power domain index. Valid values are defined in - include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and - include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc + include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc, + include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc a= nd + include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc + maxItems: 1 =20 clocks: diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings= /power/imx8mm-power.h new file mode 100644 index 000000000000..bec25fd32394 --- /dev/null +++ b/include/dt-bindings/power/imx8mm-power.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2021 Adrien Grassein + */ + +#ifndef __DT_BINDINGS_IMX8MM_POWER_H__ +#define __DT_BINDINGS_IMX8MM_POWER_H__ + +#define IMX8MM_POWER_DOMAIN_HSIOMIX 0 +#define IMX8MM_POWER_DOMAIN_PCIE1 1 +#define IMX8MM_POWER_DOMAIN_USB_OTG1 2 +#define IMX8MM_POWER_DOMAIN_USB_OTG2 3 +#define IMX8MM_POWER_DOMAIN_GPU 4 +#define IMX8MM_POWER_DOMAIN_VPU 5 +#define IMX8MM_POWER_DOMAIN_VPU_G1 6 +#define IMX8MM_POWER_DOMAIN_VPU_G2 7 +#define IMX8MM_POWER_DOMAIN_VPU_H1 8 +#define IMX8MM_POWER_DOMAIN_DISPLAY 9 +#define IMX8MM_POWER_DOMAIN_MIPI 10 + +#endif --=20 2.25.1 From nobody Thu May 2 19:03:59 2024 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1617830537; cv=none; d=zohomail.com; s=zohoarc; b=TLY3krSLJjSV/L0Qg+iEiBPI2mLBmKA+MJjBKZwwmovYlVd3X2Won9GQOGm2FivB8PjtunK4u3kHkRb3MmzPWmTExUJkY19UvPDYnDdM0lXUC5+XKe+TKGwe1UIFQEyTRkIZ7BFANFF60tE3MQY6KtrNdFkbj6+KNOxyvNvnzwk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617830537; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=p1PTOuVujSZNdb+lfDvpozibockRl2kaTT+F2J5Pasw=; b=l4+rT/oPUI0ER3Ebl1wJYnY1T67Y7Y6Zz4o6OXrubD3XLNsBbI48fM+6PTJPe6sZxGn8pHWe0DMqnxnfOZiWrrGfnraGmKjmS4HaFvub6LapL5GmhXMKjw12pikz4b885dOgB2PHjA7qc7+Y+s3Cbx5DqUbrP0Gyveu7B1OffGs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1617830537417260.1992402675801; Wed, 7 Apr 2021 14:22:17 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233005AbhDGVW0 (ORCPT ); Wed, 7 Apr 2021 17:22:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232617AbhDGVVt (ORCPT ); Wed, 7 Apr 2021 17:21:49 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9575C0613D8; Wed, 7 Apr 2021 14:21:32 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id y20-20020a1c4b140000b029011f294095d3so1856107wma.3; Wed, 07 Apr 2021 14:21:32 -0700 (PDT) Received: from adgra-XPS-15-9570.home (2a01cb0008bd270041a0a0f4308eafc0.ipv6.abo.wanadoo.fr. [2a01:cb00:8bd:2700:41a0:a0f4:308e:afc0]) by smtp.gmail.com with ESMTPSA id l14sm17173952wrm.77.2021.04.07.14.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 14:21:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p1PTOuVujSZNdb+lfDvpozibockRl2kaTT+F2J5Pasw=; b=hU+4+AJxEKpFo9IbdYWwYFG4mcGdHdQEpeyEFyR7KnYM+l3iB/6u7xPo6yYaXgJKb+ 620IFEIBHIfhYbX5Bf93myZzGJeAUopB0AlVN12TXv6B0DW0QHexQBfUCOGBMbErKELc op20ywP+ZOSEEEdLm+nZwLH3xrnF1ztziA+0m1uIVGZBdkInI1FhjEga+6QKA41YEa4g dmImneFwW3s1WCzKJBxal7MRS9X/66EJNy99Jf9TY2uKUrAU9cBIeg7rSPeKLFqqW06L 3Pkp+TBQDpdEfpdMjotT1M2XKmQgEO2SPwhp0sggPhnEBgOMg+OVKSMYW3VG+hX+YkKs r4og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p1PTOuVujSZNdb+lfDvpozibockRl2kaTT+F2J5Pasw=; b=V92UAJI8N7jegq4StekOEeHYrSqnU47WggdzgV3vyJxeI+/i7DzXSLXG/DzRScf1hL sn6vhzPK1jODPhh4xGO6r4m4+b/XxqvC1TwlL3/VWf+Zzn4F1BD8SG+a23jVcE/eUhpb Man8Gajak5j1dEI1g2M54yL75VNKB0htXlKC1+32CDAJNCujtOoBKhLjmsijfAyFaXRL ar/NNREvwNoUg+6XHL9Upo0O6CU8puFCntVh9jCnEik90vAY43efAtFdtngRpHKVfoph 90v848c8dgDrSNKXMJNUjorOwG+3OMAm/2u3K3YAs7TaUq7Pw/iKNrRPmkWrHF6yj7Sr gtew== X-Gm-Message-State: AOAM531H0hEaoGuuazd0chNGWXjG0KjxpJqxN5M2f1sf47qMcEOOjeiA W3747KhHSOZ+N1DIlDoBsXoYRjmLPx7oiA== X-Google-Smtp-Source: ABdhPJzx/PC85Ea03U9I6eTPnMVrWh7e0WLzu4mGuTVWxdV4P0bcDt0SF6lSDD1jMlDkZ4kMtB4zsQ== X-Received: by 2002:a7b:c45a:: with SMTP id l26mr4954756wmi.85.1617830491411; Wed, 07 Apr 2021 14:21:31 -0700 (PDT) From: Adrien Grassein Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, l.stach@pengutronix.de, Anson.Huang@nxp.com, krzk@kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, qiangqing.zhang@nxp.com, alice.guo@nxp.com, aford173@gmail.com, agx@sigxcpu.org, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Adrien Grassein Subject: [PATCH v1 5/7] soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM Date: Wed, 7 Apr 2021 23:21:20 +0200 Message-Id: <20210407212122.626137-6-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407212122.626137-1-adrien.grassein@gmail.com> References: <20210407212122.626137-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add description for 3 domains of the i.MX8MM: - HSIO - USB OTG 1 - USB OTG 2 Signed-off-by: Adrien Grassein --- drivers/soc/imx/gpcv2.c | 69 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index d97a53502753..571d0381dd87 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -17,6 +17,8 @@ #include #include #include +#include + =20 #define GPC_LPCR_A_CORE_BSC 0x000 =20 @@ -42,6 +44,9 @@ #define IMX8M_PCIE1_A53_DOMAIN BIT(3) #define IMX8M_MIPI_A53_DOMAIN BIT(2) =20 +#define IMX8MM_OTG2_A53_DOMAIN BIT(5) +#define IMX8MM_OTG1_A53_DOMAIN BIT(4) + #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 #define GPC_PU_PGC_SW_PDN_REQ 0x104 =20 @@ -65,6 +70,9 @@ #define IMX8M_PCIE1_SW_Pxx_REQ BIT(1) #define IMX8M_MIPI_SW_Pxx_REQ BIT(0) =20 +#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2) +#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3) + #define GPC_M4_PU_PDN_FLG 0x1bc =20 #define GPC_PU_PWRHSK 0x1fc @@ -76,6 +84,9 @@ #define IMX8M_DISP_HSK_PWRDNREQN BIT(4) #define IMX8M_DISP_HSK_PWRDNACKN BIT(24) =20 +#define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6)) +#define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24)) + /* * The PGC offset values in Reference Manual * (Rev. 1, 01/2018 and the older ones) GPC chapter's @@ -98,6 +109,9 @@ #define IMX8M_PGC_MIPI_CSI2 28 #define IMX8M_PGC_PCIE2 29 =20 +#define IMX8MM_PGC_OTG1 18 +#define IMX8MM_PGC_OTG2 19 + #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) =20 @@ -572,6 +586,60 @@ static const struct imx_pgc_domain_data imx8m_pgc_doma= in_data =3D { .reg_access_table =3D &imx8m_access_table, }; =20 +static const struct imx_pgc_domain imx8mm_pgc_domains[] =3D { + [IMX8MM_POWER_DOMAIN_HSIOMIX] =3D { + .genpd =3D { + .name =3D "hsiomix", + }, + .bits =3D { + .hsk_req =3D IMX8MM_HSIO_HSK_PWRDNREQN, + .hsk_ack =3D IMX8MM_HSIO_HSK_PWRDNACKN, + }, + }, + + [IMX8MM_POWER_DOMAIN_USB_OTG1] =3D { + .genpd =3D { + .name =3D "usb-otg1", + }, + .bits =3D { + .pxx =3D IMX8MM_OTG1_SW_Pxx_REQ, + .map =3D IMX8MM_OTG1_A53_DOMAIN, + }, + .pgc =3D IMX8MM_PGC_OTG1, + }, + + [IMX8MM_POWER_DOMAIN_USB_OTG2] =3D { + .genpd =3D { + .name =3D "usb-otg2", + }, + .bits =3D { + .pxx =3D IMX8MM_OTG2_SW_Pxx_REQ, + .map =3D IMX8MM_OTG2_A53_DOMAIN, + }, + .pgc =3D IMX8MM_PGC_OTG2, + }, +}; + +static const struct regmap_range imx8mm_yes_ranges[] =3D { + regmap_reg_range(GPC_LPCR_A_CORE_BSC, + GPC_PU_PWRHSK), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1), + GPC_PGC_SR(IMX8MM_PGC_OTG1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2), + GPC_PGC_SR(IMX8MM_PGC_OTG2)), +}; + +static const struct regmap_access_table imx8mm_access_table =3D { + .yes_ranges =3D imx8mm_yes_ranges, + .n_yes_ranges =3D ARRAY_SIZE(imx8mm_yes_ranges), +}; + +static const struct imx_pgc_domain_data imx8mm_pgc_domain_data =3D { + .domains =3D imx8mm_pgc_domains, + .domains_num =3D ARRAY_SIZE(imx8mm_pgc_domains), + .reg_access_table =3D &imx8mm_access_table, +}; + static int imx_pgc_get_clocks(struct imx_pgc_domain *domain) { int i, ret; @@ -766,6 +834,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) static const struct of_device_id imx_gpcv2_dt_ids[] =3D { { .compatible =3D "fsl,imx7d-gpc", .data =3D &imx7_pgc_domain_data, }, { .compatible =3D "fsl,imx8mq-gpc", .data =3D &imx8m_pgc_domain_data, }, + { .compatible =3D "fsl,imx8mm-gpc", .data =3D &imx8mm_pgc_domain_data, }, { } }; =20 --=20 2.25.1 From nobody Thu May 2 19:03:59 2024 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; 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[2a01:cb00:8bd:2700:41a0:a0f4:308e:afc0]) by smtp.gmail.com with ESMTPSA id l14sm17173952wrm.77.2021.04.07.14.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 14:21:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jh571+ID0yhjIhjxf9sqAGVgpEsTICaKfHEOpTGXD08=; b=OO7/w7Rh3U88gbnj2a5swi/4XoKyJHBeb76uJS6ZsEIzGK7jn/8F/b/p3UgeUSSJES 6YZqo2T/y+EVj4xDUKJH+mU/rSsOTu33xoux6JUUBpqdIbSZlL9uE7SJifDEDYLYVdfl OStIIWHsmQSd5x79KnyJhTtXjJzz42goXjCjCmW7fTvPwoCYF7n9GSC1KlBwnySXL13e XgWHyYML9S+9SMzP39XGCMeNWdGuYYbMsjHKtmxfGQVFYBzZB7J5M/QIsyKQwrC3Uo1O zkv7LBs/OM0QVkHbWiSQGOSr5GorUe4U0x5A3DjGZXASRlX+Y3h9zodVkPKj4qY1qvDm P6Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jh571+ID0yhjIhjxf9sqAGVgpEsTICaKfHEOpTGXD08=; b=UhB3gce/F6aU4uJPTUbTFsu5C8ghfm5wHX/7FesnCIX6BgevpsJALCGQ9uQbuI17sH XKn2YJwZ6jP4/O2ksB2gx6KXHjdhyz/q8KDIznUhkRthPtzfpNJRZtB2aKbpgL0q8DRB UZVCmDmf9HjK0i3R1+GzW940E1MXvRchoveRYjx08tzxH7Ij/IuXmdPrZ0eHSzqOVDRI buu/4DYmoVYG3dmV6a7QScw+lzo0efT6Tj8r8IK/cuK0GQ7R1FHxFj1IHtMqTZqArUoA wz4vpsaNOxyzGlJmytDLdi3oNMj9VW9qnMiMMH8IuSQNt1AUamSe+WmZaqI98ncqY6SC jm8Q== X-Gm-Message-State: AOAM531WL5m6ZOZrdi8dVPdWT57BTJgG0CRODbowDlsAajRq7xgPSTEM hVTA3cYWxEitFlF/Vu3nAFI= X-Google-Smtp-Source: ABdhPJziPKYKQAlsNoPeXWoU1fwTbJL91YMbyi9TaeQIh154vKLaCIaXpURz7OJrBl5pWZq719FxhQ== X-Received: by 2002:adf:cf0f:: with SMTP id o15mr6532453wrj.91.1617830492311; Wed, 07 Apr 2021 14:21:32 -0700 (PDT) From: Adrien Grassein Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, l.stach@pengutronix.de, Anson.Huang@nxp.com, krzk@kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, qiangqing.zhang@nxp.com, alice.guo@nxp.com, aford173@gmail.com, agx@sigxcpu.org, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Adrien Grassein Subject: [PATCH v1 6/7] soc: imx: gpcv2: add quirks to domains Date: Wed, 7 Apr 2021 23:21:21 +0200 Message-Id: <20210407212122.626137-7-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407212122.626137-1-adrien.grassein@gmail.com> References: <20210407212122.626137-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Some domains need quirks during their operation. For example, on i.MX8MM, USB domains should not be powered off. Signed-off-by: Adrien Grassein --- drivers/soc/imx/gpcv2.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 571d0381dd87..592b9808dcd4 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -119,6 +119,10 @@ =20 #define GPC_CLK_MAX 6 =20 +/* Quirks */ +//Refuse to poweroff the domain +#define GPC_QUIRKS_DONT_POWEROFF BIT(0) + static DEFINE_MUTEX(gpc_pd_mutex); =20 struct imx_pgc_domain { @@ -139,6 +143,7 @@ struct imx_pgc_domain { =20 const int voltage; struct device *dev; + const unsigned int quirks; }; =20 struct imx_pgc_domain_data { @@ -263,6 +268,9 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_= domain *genpd) int i, ret =3D 0; u32 value; =20 + if (domain->quirks & GPC_QUIRKS_DONT_POWEROFF) + return 0; + mutex_lock(&gpc_pd_mutex); =20 /* Enable reset clocks for all devices in the domain */ @@ -606,6 +614,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[]= =3D { .map =3D IMX8MM_OTG1_A53_DOMAIN, }, .pgc =3D IMX8MM_PGC_OTG1, + .quirks =3D GPC_QUIRKS_DONT_POWEROFF, }, =20 [IMX8MM_POWER_DOMAIN_USB_OTG2] =3D { @@ -617,6 +626,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[]= =3D { .map =3D IMX8MM_OTG2_A53_DOMAIN, }, .pgc =3D IMX8MM_PGC_OTG2, + .quirks =3D GPC_QUIRKS_DONT_POWEROFF, }, }; =20 --=20 2.25.1 From nobody Thu May 2 19:03:59 2024 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1617830539; cv=none; d=zohomail.com; s=zohoarc; b=fgqG22sKA+YuKt/ugb8ZMvbu9opZaqegFf0gkyxKq0NXRdA/isGLQ8ncmkZQ7L+RO67dVsYAWExVdd9b15rlv+QsSEO6JWHJvlVZbviCFWxgwekk2ZRtTkLJ25HxGY0DgK1LTYT1YO5BRokvlVzXvkYTPb91r2R0yUjaVqm8iPQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1617830539; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Subject:To; bh=NtFOY3jGwpepTPbYEqh8kZlA1Mb2wn1W95xoHay4I/4=; b=TQIPlcUXl5xLDwhVRHbnRowrRAMz2WgGOGiM7w1KEqYkqMNu4vNiR1IaVnKKodG/fxuyfdajw2KYxH9YGjU1Qy5NHAJise0gyPwPJz1g+acUq6Dj0Nx0eoelbVREsamrnWM6HlgO5yjRMa1bknwsrprEoT6wKBv4oESsvGgnPC4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1617830539062565.1786492236989; Wed, 7 Apr 2021 14:22:19 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232789AbhDGVW2 (ORCPT ); Wed, 7 Apr 2021 17:22:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232649AbhDGVVy (ORCPT ); Wed, 7 Apr 2021 17:21:54 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D96DCC0613D9; Wed, 7 Apr 2021 14:21:34 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id a12so9668496wrq.13; Wed, 07 Apr 2021 14:21:34 -0700 (PDT) Received: from adgra-XPS-15-9570.home (2a01cb0008bd270041a0a0f4308eafc0.ipv6.abo.wanadoo.fr. [2a01:cb00:8bd:2700:41a0:a0f4:308e:afc0]) by smtp.gmail.com with ESMTPSA id l14sm17173952wrm.77.2021.04.07.14.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 14:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NtFOY3jGwpepTPbYEqh8kZlA1Mb2wn1W95xoHay4I/4=; b=OgamkSyW+w07gNRyBMzhT94ZSxA0yKZVKdEjFwHwUpzS6iGTdn34mjv7A+ziE/ulq5 HOGoiJ2aFpqW1xD/Y8ht2WVO9TwARKC5NviF+0i+gwf0MM4iyh9abIFDk283mRNT1LEc k+P2DmtY8FxPLMMX3nwrJz6D7jerBZZel0Clx9id1q1x34h7V5Fgxx1T8iTkNS2JcmvV y1G2BFSy8DWzo0RPfzjlVkgEk/hYm+z7Nzo6ltDZ/koNoiOgz+nZP7gSFuZ/Snz9ADg6 0yvJs2cTNeOq2Dbb+0ZcY5i/ft7P1xANBQHfrEi9jWzBpKBJ3GLc0a0sDPSb8Vv6n8Np i5Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NtFOY3jGwpepTPbYEqh8kZlA1Mb2wn1W95xoHay4I/4=; b=PN9nzzSqt6Cferd1wWc45cw/y/JcOYx7ftRUk3mVdzRf5ugpfBKRl46XBJ/pv2vmU9 XOd2ZEQKiZwgXl/mOSNb3ddev0zRbxOfPFRQOuGTwAcjWF5jpmAzAO9DA2QTBELXAP+B CA/VuX6OBUwtrbbHsKDGNiDeaLEix79hioKHif0DsRRkK775XZrY7FkT3SI4L5UaFnfM OWbTK+QTHUScscyzZnNz3cqJtwC01dRG1EhoVVwXa8tfQ7M4rChk4wzgexflJ1tk43hs DELfHWXShOc+ZwyCYPJq8srdpM0a/rKBimZSErZVfIRsbMb/uHn4wtA8qX/pCAoj+uaE NXGA== X-Gm-Message-State: AOAM530er/Mn3xDYHYgRzW70oo6B9MGojnowQVCva5tfhui5dUg/ccae b+lT2yJq0hwI/jCua0Yop8M= X-Google-Smtp-Source: ABdhPJwWolRKrmT5Do1plHObMIKs81M84YmjT2qaELjqxjXDo7Tr3gWVDmkiHXMDIA+/aVCR8YuFYw== X-Received: by 2002:a5d:6152:: with SMTP id y18mr6699744wrt.255.1617830493687; Wed, 07 Apr 2021 14:21:33 -0700 (PDT) From: Adrien Grassein Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, l.stach@pengutronix.de, Anson.Huang@nxp.com, krzk@kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, qiangqing.zhang@nxp.com, alice.guo@nxp.com, aford173@gmail.com, agx@sigxcpu.org, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Adrien Grassein Subject: [PATCH v1 7/7] arm64: dts: imx8mm: add power-domains Date: Wed, 7 Apr 2021 23:21:22 +0200 Message-Id: <20210407212122.626137-8-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407212122.626137-1-adrien.grassein@gmail.com> References: <20210407212122.626137-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add description for HSIO and USB power-domains. Signed-off-by: Adrien Grassein --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index a27e02bee6b4..028b8930db5a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -600,6 +601,38 @@ src: reset-controller@30390000 { interrupts =3D ; #reset-cells =3D <1>; }; + + gpc: gpc@303a0000 { + compatible =3D "fsl,imx8mm-gpc"; + reg =3D <0x303a0000 0x10000>; + interrupts =3D ; + interrupt-parent =3D <&gic>; + interrupt-controller; + #interrupt-cells =3D <3>; + + pgc { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pgc_hsiomix: power-domain@IMX8MM_POWER_DOMAIN_HSIOMIX { + #power-domain-cells =3D <0>; + reg =3D ; + clocks =3D <&clk IMX8MM_CLK_USB_BUS>; + }; + + pgc_usb_otg1: power-domain@IMX8MM_POWER_DOMAIN_USB_OTG1 { + #power-domain-cells =3D <0>; + reg =3D ; + power-domains =3D <&pgc_hsiomix>; + }; + + pgc_usb_otg2: power-domain@IMX8MM_POWER_DOMAIN_USB_OTG2 { + #power-domain-cells =3D <0>; + reg =3D ; + power-domains =3D <&pgc_hsiomix>; + }; + }; + }; }; =20 aips2: bus@30400000 { @@ -953,6 +986,7 @@ usbotg1: usb@32e40000 { assigned-clock-parents =3D <&clk IMX8MM_SYS_PLL2_500M>; fsl,usbphy =3D <&usbphynop1>; fsl,usbmisc =3D <&usbmisc1 0>; + power-domains =3D <&pgc_usb_otg1>; status =3D "disabled"; }; =20 @@ -972,6 +1006,7 @@ usbotg2: usb@32e50000 { assigned-clock-parents =3D <&clk IMX8MM_SYS_PLL2_500M>; fsl,usbphy =3D <&usbphynop2>; fsl,usbmisc =3D <&usbmisc2 0>; + power-domains =3D <&pgc_usb_otg2>; status =3D "disabled"; }; =20 --=20 2.25.1