From nobody Fri May 9 23:16:37 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=quarantine dis=quarantine) header.from=ti.com ARC-Seal: i=1; a=rsa-sha256; t=1620726842; cv=none; d=zohomail.com; s=zohoarc; b=gMyNmWRZ3Hh4YXEDi4z+ziCtL3+eoAUyiCv5MLtIJKN7Iy7Ozmkz1fXrPNwk1RcEBLU5qWiXZE3xF22AUO7zeL0RwoxguxHb/ZmEdpA4nTXPalGsw0cly6iTDPTvAgp1RzcOq6dKUgi1RMK9b8X+XhpvWx5CoNeg+QiQmNIUUj0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620726842; h=Content-Type:Cc:Date:From:List-Id:MIME-Version:Message-ID:Subject:To; bh=z9UAR+/RmS3yDyR1l995bN55sFL4hrr9lxH1F4VEQjY=; b=XsSyr6pZyt0b0DcLYsrTiF+ICoUClfQa5aD+IGUIoXaZ7L2g1fh6/lpaZgFoz2GoHNlhA7w4hHan9P0vVX99yQPiGisHLe011ZAL4YS1zMWzmmseoSCZVtMqXDNbg1ER8dlmajIA3gSLM+cufPIFkGfSsd5YtpPNNklVIzM2IJw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=quarantine dis=quarantine) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1620726842025415.38449618046957; Tue, 11 May 2021 02:54:02 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231220AbhEKJzG (ORCPT ); Tue, 11 May 2021 05:55:06 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:43496 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231189AbhEKJzE (ORCPT ); Tue, 11 May 2021 05:55:04 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14B9roQ6110601; Tue, 11 May 2021 04:53:50 -0500 Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14B9roRt123002 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 11 May 2021 04:53:50 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 11 May 2021 04:53:49 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 11 May 2021 04:53:49 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14B9rfrn089715; Tue, 11 May 2021 04:53:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1620726830; bh=z9UAR+/RmS3yDyR1l995bN55sFL4hrr9lxH1F4VEQjY=; h=From:To:CC:Subject:Date; b=cm46Afi4XVnDWcwhl5s9KL0Iy6F6+I+WbF9BVo3ajfVOkywNACexJC4IY0CjjwY2F m4KKWk6m/5xJUWzWYWEkZ7dgRuNhTIgDfaj3A6a2Jq1sSiTzSC9WzFw6fBPZjhT+oY K48yBApcghSnnsqY2vaJFR/QApUSWCRij2ryncGI= From: Aswath Govindraju CC: Vignesh Raghavendra , Lokesh Vutla , Kishon Vijay Abraham I , Jan Kiszka , Aswath Govindraju , Nishanth Menon , Tero Kristo , Rob Herring , , , Subject: [PATCH v2] arm64: dts: ti: k3-am65: Add support for UHS-I modes in MMCSD1 subsystem Date: Tue, 11 May 2021 15:23:39 +0530 Message-ID: <20210511095339.16268-1-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" UHS-I speed modes are supported in AM65 S.R. 2.0 SoC[1]. Add support by removing the no-1-8-v tag and including the voltage regulator device tree nodes for power cycling. However, the 4 bit interface of AM65 SR 1.0 cannot be supported at 3.3 V or 1.8 V because of erratas i2025 and i2026 [2]. As the SD card is the primary boot mode for development usecases, continue to enable SD card and disable UHS-I modes in it to minimize any ageing issues happening because of erratas. k3-am6528-iot2050-basic and k3-am6548-iot2050-advanced boards use S.R. 1.0 version of AM65 SoC. Therefore, add no-1-8-v in sdhci1 device tree nodes for these boards. [1] - https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf, section 12.3.6.1.1 [2] - https://www.ti.com/lit/er/sprz452e/sprz452e.pdf Signed-off-by: Aswath Govindraju --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 - .../boot/dts/ti/k3-am6528-iot2050-basic.dts | 4 +++ .../arm64/boot/dts/ti/k3-am654-base-board.dts | 33 +++++++++++++++++++ .../dts/ti/k3-am6548-iot2050-advanced.dts | 4 +++ 4 files changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index cb340d1b401f..632f32fce4a1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -301,7 +301,6 @@ ti,otap-del-sel =3D <0x2>; ti,trm-icp =3D <0x8>; dma-coherent; - no-1-8-v; }; =20 scm_conf: scm-conf@100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts b/arch/arm6= 4/boot/dts/ti/k3-am6528-iot2050-basic.dts index 4f7e3f2a6265..485266960d5f 100644 --- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts +++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts @@ -40,6 +40,10 @@ status =3D "disabled"; }; =20 +&sdhci1 { + no-1-8-v; +}; + &main_pmx0 { main_uart0_pins_default: main-uart0-pins-default { pinctrl-single,pins =3D < diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index 9e87fb313a54..51c594b4dddb 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -91,6 +91,38 @@ #clock-cells =3D <0>; clock-frequency =3D <24000000>; }; + + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible =3D "regulator-fixed"; + regulator-name =3D "evm_12v0"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_io: fixedregulator-vcc3v3io { + /* Output of TPS54334 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_io"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&evm_12v0>; + }; + + vdd_mmc1_sd: fixedregulator-sd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1_sd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply =3D <&vcc3v3_io>; + gpio =3D <&pca9554 4 GPIO_ACTIVE_HIGH>; + }; }; =20 &wkup_pmx0 { @@ -350,6 +382,7 @@ * disable sdhci1 */ &sdhci1 { + vmmc-supply =3D <&vdd_mmc1_sd>; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc1_pins_default>; ti,driver-strength-ohm =3D <50>; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts b/arch/a= rm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts index ec9617c13cdb..3643a19b5f33 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts @@ -55,6 +55,10 @@ disable-wp; }; =20 +&sdhci1 { + no-1-8-v; +}; + &main_uart0 { status =3D "disabled"; }; --=20 2.17.1