From nobody Fri May 9 23:21:52 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=quarantine dis=quarantine) header.from=ti.com ARC-Seal: i=1; a=rsa-sha256; t=1620751749; cv=none; d=zohomail.com; s=zohoarc; b=TG8qu8IzIAFLxv7WSckBQilXnCd7EWjuFTGmX3D+jgOcUobRh+VEALEsQiEJK93+W/Ql3o11jbYIiw7URQ5R+BiKlXYRx1tKlendPWyq1wU1qB/1KiWwSlPIT0y0rwRlHiwucjFXuUgj2TwDadazKclOZ/MVLN4c/rfdLd3lTgg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620751749; h=Content-Type:Cc:Date:From:List-Id:MIME-Version:Message-ID:Subject:To; bh=EXAHHMVat87Ts4QpaLnkvfakXOyXP0EushBlIk4YxAU=; b=gOPMNxxTZSPNJ9bKoCe/XCtb8/6v9iJU3ebLuSuLIQF4WkNLeSQJigacMoNEMiwgB973Z6T8URarHVTLxfw+Oorp0HyCOv7cD+ui7/hNbs04Utzcpnj3+Sr8Z1Xw/9o10oNmeSJr1kFwvRAOS2LEEKH6Js9sZiQ+o7uuQMCIwQQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail header.from= (p=quarantine dis=quarantine) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1620751749551911.9071487327677; Tue, 11 May 2021 09:49:09 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231435AbhEKQuO (ORCPT ); Tue, 11 May 2021 12:50:14 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54290 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230435AbhEKQuM (ORCPT ); Tue, 11 May 2021 12:50:12 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14BGmxsf009587; Tue, 11 May 2021 11:48:59 -0500 Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14BGmx0j118266 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 11 May 2021 11:48:59 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 11 May 2021 11:48:58 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 11 May 2021 11:48:58 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14BGmpjT012233; Tue, 11 May 2021 11:48:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1620751739; bh=EXAHHMVat87Ts4QpaLnkvfakXOyXP0EushBlIk4YxAU=; h=From:To:CC:Subject:Date; b=V24NP39TD9uOX4Lr4LCxTO9F5JHfnVY7ADK/udWXy3Zp97C/pck+P6lCl2Qi4gqlT xGDySaKjuD5mTIQ5Lntqnmk4a2bvsBWRMRzz/eQCWhXu8jFVl57KptsoVbs18rtKEc oY+vwqode2qcmtZPNXEOmCuvgFQUWGzEzbD1X9rw= From: Aswath Govindraju CC: Vignesh Raghavendra , Lokesh Vutla , Kishon Vijay Abraham I , Jan Kiszka , Aswath Govindraju , Nishanth Menon , Tero Kristo , Rob Herring , , , Subject: [PATCH v3] arm64: dts: ti: k3-am65: Add support for UHS-I modes in MMCSD1 subsystem Date: Tue, 11 May 2021 22:18:49 +0530 Message-ID: <20210511164849.20016-1-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" UHS-I speed modes are supported in AM65 S.R. 2.0 SoC[1]. Add support by removing the no-1-8-v tag and including the voltage regulator device tree nodes for power cycling. However, the 4 bit interface of AM65 SR 1.0 cannot be supported at 3.3 V or 1.8 V because of erratas i2025 and i2026 [2]. As the SD card is the primary boot mode for development usecases, continue to enable SD card and disable UHS-I modes in it to minimize any ageing issues happening because of erratas. k3-am6528-iot2050-basic and k3-am6548-iot2050-advanced boards use S.R. 1.0 version of AM65 SoC. Therefore, add no-1-8-v in sdhci1 device tree node of the common iot2050 device tree file. [1] - https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf, section 12.3.6.1.1 [2] - https://www.ti.com/lit/er/sprz452e/sprz452e.pdf Signed-off-by: Aswath Govindraju --- changes since v2: - moved the no-1-8-v tag to common iot2050 dtsi file. changes since v1: - added no-1-8-v tag in sdhci1 dt nodes of k3-am6528-iot2050-basic and k3-am6548-iot2050-advanced boards as they use S.R.1.0 version AM65 SoC. .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 - .../arm64/boot/dts/ti/k3-am654-base-board.dts | 33 +++++++++++++++++++ 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index de763ca9251c..46cc348cd4be 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -555,6 +555,7 @@ pinctrl-0 =3D <&main_mmc1_pins_default>; ti,driver-strength-ohm =3D <50>; disable-wp; + no-1-8-v; }; =20 &usb0 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index cb340d1b401f..632f32fce4a1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -301,7 +301,6 @@ ti,otap-del-sel =3D <0x2>; ti,trm-icp =3D <0x8>; dma-coherent; - no-1-8-v; }; =20 scm_conf: scm-conf@100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index 9e87fb313a54..51c594b4dddb 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -91,6 +91,38 @@ #clock-cells =3D <0>; clock-frequency =3D <24000000>; }; + + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible =3D "regulator-fixed"; + regulator-name =3D "evm_12v0"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_io: fixedregulator-vcc3v3io { + /* Output of TPS54334 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_io"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&evm_12v0>; + }; + + vdd_mmc1_sd: fixedregulator-sd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1_sd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply =3D <&vcc3v3_io>; + gpio =3D <&pca9554 4 GPIO_ACTIVE_HIGH>; + }; }; =20 &wkup_pmx0 { @@ -350,6 +382,7 @@ * disable sdhci1 */ &sdhci1 { + vmmc-supply =3D <&vdd_mmc1_sd>; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc1_pins_default>; ti,driver-strength-ohm =3D <50>; --=20 2.17.1