From nobody Sat May 10 01:53:08 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=quarantine dis=quarantine) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1627294244212133.49839044777843; Mon, 26 Jul 2021 03:10:44 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233214AbhGZJaN (ORCPT ); Mon, 26 Jul 2021 05:30:13 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:44536 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233195AbhGZJaI (ORCPT ); Mon, 26 Jul 2021 05:30:08 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16QAAUQb009367; Mon, 26 Jul 2021 05:10:30 -0500 Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16QAAUoR126687 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 26 Jul 2021 05:10:30 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Mon, 26 Jul 2021 05:10:29 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 26 Jul 2021 05:10:29 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16QAACRg067730; Mon, 26 Jul 2021 05:10:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1627294230; bh=NR5oZE1dQLKGhgVkd9kYgep95NgSMqu07wy/D4cS5vg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I1CYwiwANRZJlGKL29K2KMn6Rln9T8I3TLsJ3JEJuZhzndc8oVpZUNOHFexsGtiJi E2u5N8xP8PR2ZYSJn2L8hghMsDGWP5CJXbIM3hHKGFPotCn0opXxnbjNL9SkZlqJ3O Rj9trFZulDTBdK0KJjdL3HC7Npx99pSnqU+xN6H0= From: Aswath Govindraju CC: , , , Nishanth Menon , Tero Kristo , Rob Herring , Marc Kleine-Budde , Lokesh Vutla , Faiz Abbas , Aswath Govindraju Subject: [PATCH v2 3/6] arm64: dts: ti: k3-j721e: Add support for MCAN nodes Date: Mon, 26 Jul 2021 15:40:09 +0530 Message-ID: <20210726101012.26983-4-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210726101012.26983-1-a-govindraju@ti.com> References: <20210726101012.26983-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1627294244832100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Faiz Abbas Add support for 14 MCAN controllers in main domain and 2 MCAN controllers present in mcu domain. All the MCAN controllers support classic CAN messages as well as CAN_FD messages. Signed-off-by: Faiz Abbas Signed-off-by: Aswath Govindraju --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 196 ++++++++++++++++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 28 +++ 2 files changed, 224 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index cf3482376c1e..43080f62a612 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1940,4 +1940,200 @@ bus_freq =3D <1000000>; }; }; + + main_mcan0: can@2701000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x02701000 0x00 0x200>, + <0x00 0x02708000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 156 1>, <&k3_clks 156 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan1: can@2711000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x02711000 0x00 0x200>, + <0x00 0x02718000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 158 1>, <&k3_clks 158 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan2: can@2721000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x02721000 0x00 0x200>, + <0x00 0x02728000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 160 1>, <&k3_clks 160 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan3: can@2731000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x02731000 0x00 0x200>, + <0x00 0x02738000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 161 1>, <&k3_clks 161 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan4: can@2741000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x02741000 0x00 0x200>, + <0x00 0x02748000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 162 1>, <&k3_clks 162 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan5: can@2751000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x02751000 0x00 0x200>, + <0x00 0x02758000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 163 1>, <&k3_clks 163 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan6: can@2761000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x02761000 0x00 0x200>, + <0x00 0x02768000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 164 1>, <&k3_clks 164 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan7: can@2771000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x02771000 0x00 0x200>, + <0x00 0x02778000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 165 1>, <&k3_clks 165 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan8: can@2781000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x02781000 0x00 0x200>, + <0x00 0x02788000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 166 1>, <&k3_clks 166 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan9: can@2791000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x02791000 0x00 0x200>, + <0x00 0x02798000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 167 1>, <&k3_clks 167 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan10: can@27a1000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x027a1000 0x00 0x200>, + <0x00 0x027a8000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 168 1>, <&k3_clks 168 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan11: can@27b1000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x027b1000 0x00 0x200>, + <0x00 0x027b8000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 169 1>, <&k3_clks 169 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan12: can@27c1000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x027c1000 0x00 0x200>, + <0x00 0x027c8000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 170 1>, <&k3_clks 170 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan13: can@27d1000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x027d1000 0x00 0x200>, + <0x00 0x027d8000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 171 1>, <&k3_clks 171 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index d2dceda72fe9..a8dbd843b002 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -390,4 +390,32 @@ ti,loczrama =3D <1>; }; }; + + mcu_mcan0: can@40528000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x40528000 0x00 0x200>, + <0x00 0x40500000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 172 1>, <&k3_clks 172 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; + + mcu_mcan1: can@40568000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x40568000 0x00 0x200>, + <0x00 0x40540000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 173 1>, <&k3_clks 173 0>; + clock-names =3D "cclk", "hclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + }; }; --=20 2.17.1