From nobody Tue Feb 10 18:38:20 2026 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=quarantine dis=quarantine) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1643116653227872.4358314075696; Tue, 25 Jan 2022 05:17:33 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1576164AbiAYNRL (ORCPT ); Tue, 25 Jan 2022 08:17:11 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:56474 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1575773AbiAYNLu (ORCPT ); Tue, 25 Jan 2022 08:11:50 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 20PDBWM0037021; Tue, 25 Jan 2022 07:11:32 -0600 Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 20PDBVpE030095 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 25 Jan 2022 07:11:32 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 25 Jan 2022 07:11:31 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 25 Jan 2022 07:11:31 -0600 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 20PDBE3B032789; Tue, 25 Jan 2022 07:11:29 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1643116292; bh=F2FHXfQIty0qVKJxsllsCd5bWxGYr2/jjWpmX8HOjMs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=i+mPjWuFV6yasYnGIb5q0rkQqS7wQav1YUeFY9ekz0+0AwA1Eeri09yDlUfdfrhw7 p601cFNbVFLXjd7n3cILN9uv0jdiNAjyxtnceeM/r+a0EYy6UkoXHtNZkAIxRAwPSU tDBy1gOaMz8WGwvB5I/1HfGPyWjKqQbrQ0J35+8c= From: Aswath Govindraju CC: , , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , Aswath Govindraju Subject: [PATCH 6/6] arm64: dts: k3-j721s2: Add support for OSPI Flashes Date: Tue, 25 Jan 2022 18:41:13 +0530 Message-ID: <20220125131113.727-7-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220125131113.727-1-a-govindraju@ti.com> References: <20220125131113.727-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643116656112100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a QSPI NOR flash on the common processor board connected to the OSPI1 instance. Add support for the same Signed-off-by: Aswath Govindraju --- .../dts/ti/k3-j721s2-common-proc-board.dts | 34 +++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index aa75dc541842..cb99a97af426 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -206,6 +206,20 @@ J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >; }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + >; + }; }; =20 &main_gpio2 { @@ -394,6 +408,26 @@ maximum-speed =3D "high-speed"; }; =20 +&ospi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <1>; + spi-rx-bus-width =3D <4>; + spi-max-frequency =3D <40000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; +}; + &mcu_mcan0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_mcan0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index 76f0ceacb6d4..a05c17dd69b6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -39,6 +39,28 @@ }; }; =20 +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ + J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins =3D < @@ -78,6 +100,26 @@ phys =3D <&transceiver0>; }; =20 +&ospi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <8>; + spi-rx-bus-width =3D <8>; + spi-max-frequency =3D <25000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; +}; + &mailbox0_cluster0 { status =3D "disabled"; }; --=20 2.17.1