From nobody Tue Feb 10 18:38:28 2026 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=quarantine dis=quarantine) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1643116733824142.99430729829362; Tue, 25 Jan 2022 05:18:53 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1576248AbiAYNSp (ORCPT ); Tue, 25 Jan 2022 08:18:45 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:56596 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1575806AbiAYNMl (ORCPT ); Tue, 25 Jan 2022 08:12:41 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 20PDCWNL037183; Tue, 25 Jan 2022 07:12:32 -0600 Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 20PDCVHV030990 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 25 Jan 2022 07:12:32 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 25 Jan 2022 07:12:31 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 25 Jan 2022 07:12:31 -0600 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 20PDCPWE008001; Tue, 25 Jan 2022 07:12:29 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1643116352; bh=VOyq+81USSsidTXpTspuPB4lfGW+i6cGdLVbOdeI7dQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=J5Ja9ZtoCy9A+OVABPQHbSlnjEL6lm5YB+cehKlFqPCuzxw1mBDfAAUuBDdP0n9uN xZ5gD4J2BAzk2J2Ih64C2aJDl0lHEOY5/13TmfAJbN+FNfnXwIpi3rgzPWnQKy20sA KALha8YsKsktURcNaZbvUlJGandqk/UQd24fhWYs= From: Aswath Govindraju CC: , , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , Kishon Vijay Abraham I , Aswath Govindraju Subject: [PATCH 1/2] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Date: Tue, 25 Jan 2022 18:42:24 +0530 Message-ID: <20220125131225.871-2-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220125131225.871-1-a-govindraju@ti.com> References: <20220125131225.871-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643116736339100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PCIe device tree node (both RC and EP) for the single PCIe instance present in j721s2. Signed-off-by: Aswath Govindraju --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index ebd55032e59c..dc365a1880d0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -795,6 +795,54 @@ }; }; =20 + pcie1_rc: pcie@2910000 { + compatible =3D "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 41>; + clock-names =3D "fck"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb013>; + msi-map =3D <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible =3D "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 41>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.17.1