From nobody Fri May 3 12:43:17 2024 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail(p=quarantine dis=quarantine) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1643274164222126.69972336488013; Thu, 27 Jan 2022 01:02:44 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238148AbiA0JCn (ORCPT ); Thu, 27 Jan 2022 04:02:43 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:59486 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238149AbiA0JCl (ORCPT ); Thu, 27 Jan 2022 04:02:41 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 20R92YDD024483; Thu, 27 Jan 2022 03:02:34 -0600 Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 20R92Y2u055004 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 27 Jan 2022 03:02:34 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 27 Jan 2022 03:02:34 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 27 Jan 2022 03:02:34 -0600 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 20R92V8E037534; Thu, 27 Jan 2022 03:02:32 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1643274154; bh=R4xctapbqo6/4l6vi9qS7z3GpL4CiuP6lFnR0Fc/VJ4=; h=From:To:CC:Subject:Date; b=I7/qzCzP/mrVX/S7v3rUWXHF7IXOxNl8S0UwdNC2ETQT+6VQO0O02yNLVuTurPHpU nEXz+ykew5cKchGupRINoLEkoxEYZZ5r3Tf/50Uv+KkpW/DhgQAVCh218yahL3aPgU 0dMCzi1wpRGFSQTrf1xupSuzIgmjeufd/sY0k9iY= From: Aswath Govindraju CC: Aswath Govindraju , Swapnil Jakhade , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , , , Subject: [PATCH] arm64: dts: ti: k3-j721e-common-proc-board: Enable PCIe + QSGMII multilink configuration Date: Thu, 27 Jan 2022 14:32:25 +0530 Message-ID: <20220127090226.11481-1-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1643274165581100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Swapnil Jakhade Enable PCIe + QSGMII multilink configuration for serdes 0. This is for testing Sierra PHY multilink configuration. Add support for PLL_CMNLC1 to get clock from REFRCV1 for multilink case. Signed-off-by: Swapnil Jakhade Signed-off-by: Aswath Govindraju --- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2d7596911b27..157d86dc2824 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -431,7 +431,7 @@ }; =20 &serdes_ln_ctrl { - idle-states =3D , , + idle-states =3D , , , , , , , , @@ -757,8 +757,8 @@ }; =20 &serdes0 { - assigned-clocks =3D <&serdes0 CDNS_SIERRA_PLL_CMNLC>; - assigned-clock-parents =3D <&wiz0_pll1_refclk>; + assigned-clocks =3D <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIER= RA_PLL_CMNLC1>; + assigned-clock-parents =3D <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>; =20 serdes0_pcie_link: phy@0 { reg =3D <0>; @@ -767,6 +767,15 @@ cdns,phy-type =3D ; resets =3D <&serdes_wiz0 1>; }; + + serdes0_qsgmii_link: phy@1 { + reg =3D <1>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 2>; + }; + }; =20 &serdes1 { --=20 2.17.1