From nobody Sat May 10 05:52:33 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612273411; cv=none; d=zohomail.com; s=zohoarc; b=f6h9HPqo6Sc9iLuFwraBjtDCJVqjufUPu7Cw8S8v/qmCaSXQJAmjctXFnB03Uxnj30O516S8Qu8TydfkqWYatE/emXAE5LitTFcVPCHMW/Qyocknmjp9NyDMD+5mwZWEP71Zc9tTBp1BTkRh4E4/trcdA9wF9pKR2raEjIL/Ikg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612273411; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4NVx4zYhThKjDiR2KqAh3vyoT2Z3TCZPW4RQDQsG50Q=; b=RPk4JZQt6oI6R06XSQvIglrp89JWUv0wr0bRdirfxvY/SE7jCexUdjsaDhmzCKJiRJyaJP/uC6FGlXHzqKjt+0DSL34wRS4yMR4/yXNRbBgXaMSD0YvEheesIVsBl5b/NxZVaAVYp7nqyA1IVH9MVmgyHKzzpnHNtWZAiUqPxnU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 161227341111781.41387126479879; Tue, 2 Feb 2021 05:43:31 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232566AbhBBNm5 (ORCPT ); Tue, 2 Feb 2021 08:42:57 -0500 Received: from mail.kernel.org ([198.145.29.99]:59602 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232355AbhBBNb2 (ORCPT ); Tue, 2 Feb 2021 08:31:28 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id E2C3F64F68; Tue, 2 Feb 2021 13:30:01 +0000 (UTC) Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011yv-KY; Tue, 02 Feb 2021 14:29:59 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=0k8G1hBpz4Np2I1ZDNqtU5gVCYWWxmCauHG4Ld/0WK8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B4qfx5bMt2weX0iSbqs43jbBq7MKFCkC+FAJ01PO13+R8QCwYAebtYke1AoVPZk9x bZuEFcOZHpH+IiAsJI1oTiGuJi6ou9tmvb1lV4y9zEWI0HOixjPBw9XQNYfDbNJeZy aMhJkU15oINMOcElK36EbUDelf3C/SLz4UIaNbg6RJgrIDxOlYIIIrcSgM/t/ATC9l 9BBrR5GqhEHcxfONkpUSkWOTUgoR89XtR2VJvNGRHnjzYKlxLHvQm4TzF1fDtokOvd Kt5epQ4fiFS4iuE9AC2T9ql1IiZcBs+kpLmjjh6C2jOmDQWuX5H9/rEjjETWRR53sD 5TJxwRQP/HImA== From: Mauro Carvalho Chehab Cc: Manivannan Sadhasivam , Rob Herring , Wei Xu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH 05/13] arm64: dts: hisilicon: Add HI3670 PCI-E controller support Date: Tue, 2 Feb 2021 14:29:50 +0100 Message-Id: <301bbde15f7a248222745c8ab98c0e20ae877db0.1612271903.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Manivannan Sadhasivam Add PCI-E controller support for HiSilicon HI3670 SoC. [mchehab+huawei@kernel.org: fix merge conflicts] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 64 +++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dt= s/hisilicon/hi3670.dtsi index 5522a5de07a8..c0a0336a8ea4 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { #clock-cells =3D <1>; }; =20 + pmctrl: pmctrl@fff31000 { + compatible =3D "hisilicon,hi3670-pmctrl", "syscon"; + reg =3D <0x0 0xfff31000 0x0 0x1000>; + #clock-cells =3D <1>; + }; + iomcu: iomcu@ffd7e000 { compatible =3D "hisilicon,hi3670-iomcu", "syscon"; reg =3D <0x0 0xffd7e000 0x0 0x1000>; @@ -660,6 +666,64 @@ gpio28: gpio@fff1d000 { clock-names =3D "apb_pclk"; }; =20 + its_pcie: interrupt-controller@f4000000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + reg =3D <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie@f4000000 { + compatible =3D "hisilicon,kirin970-pcie", "hisilicon,kirin960-pcie"; + reg =3D <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xfc000000 0x0 0x80000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names =3D "dbi", "apb", "phy", "config"; + bus-range =3D <0x0 0x1>; + msi-parent =3D <&its_pcie>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges =3D <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes =3D <1>; + #interrupt-cells =3D <1>; + interrupts =3D <0 283 4>; + interrupt-names =3D "msi"; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names =3D "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + switch,reset-gpios =3D <&gpio7 0 0 >; + eth,reset-gpios =3D <&gpio25 2 0 >; + m_2,reset-gpios =3D <&gpio3 1 0 >; + mini1,reset-gpios =3D <&gpio27 4 0 >; + + eth,clkreq-gpios =3D <&gpio20 6 0 >; + m_2,clkreq-gpios =3D <&gpio27 3 0 >; + mini1,clkreq-gpios =3D <&gpio17 0 0 >; + + /*vboost iboost pre post main*/ + eye_param =3D <0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_clkreq_pmx_func &pcie_clkreq_cfg_func>; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible =3D "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; --=20 2.29.2