From nobody Sat May 10 06:45:46 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612335809; cv=none; d=zohomail.com; s=zohoarc; b=e6uNk/tieFwSLRmNiTlkwZcf5DFyEVSjOMjzYZEots8KkIXEiLD2jSIMJ6iPbmXRx/FZEhjHIS9XbHdnaM/3FgIjBlexh4q12O3UvpaPGCw7dXa5tAdNCjMANJB1tePNeFSJFtPXJzRyJZUf9ppn688BQYscMP3rQ3m3oxVhBwU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612335809; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ae8BrAxUrDoBcWHevUN5uHpe5C2s71/wWBK5MzWumg8=; b=TlNFCpILpr0TmIG49uP5mvxORZ4MQXJmpzrm6DGvTlwC42g/pbFf3Rxl2u7XCQBrEJvMa9vr8dmiQI+856s5Se/t05b+jBV4wwWJqR6MQJbd15vOnICD05qfE9k5dMagtmHvSE5nO3BYemyuhgL+eyXQWV5xM5bGWhenSuKseTs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1612335809642616.8401340491444; Tue, 2 Feb 2021 23:03:29 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231705AbhBCHDM (ORCPT ); Wed, 3 Feb 2021 02:03:12 -0500 Received: from mail.kernel.org ([198.145.29.99]:34052 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231542AbhBCHCl (ORCPT ); Wed, 3 Feb 2021 02:02:41 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5CAF164F5D; Wed, 3 Feb 2021 07:02:00 +0000 (UTC) Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l7CAo-001CAS-1k; Wed, 03 Feb 2021 08:01:58 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612335720; bh=E7yUqQo8Xn6JFXZwfNI1IGv93ZrxMNRZcf6mv6VtGWY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iuhKsqo+otYUgU/fiLZBZYudsjQYEMq+U1nY2q51juNEp1wLW8Nt2NNSWCE5K7E58 knbIl41FPMlMspDz6AEZ0ogi4GVxkrBZx+GpXNRnpQMKLL0ckZ2pd6096GFMgR6uUM 6ZsOMihsfokZhiTxoGhROsr8Vzzx4+rdDjx9bWR276VCwS9VH8S91w6N8TRis6dJpX Yhquj7aZZn4SZ2oTv0UFdNLtQpcnGZl2p56HLbb6wvPGe9cAPOawpkhEvsspMqg5QV ej+h7+ABq2QHAQI3Z+7pQcbBQnq6xEgXuEodWc1Xs1la+Mfgd4sxdMJgtGJyJXGRA4 tJlVSkAmDrz4Q== From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 02/11] doc: bindings: kirin-pcie.txt: convert it to YAML Date: Wed, 3 Feb 2021 08:01:46 +0100 Message-Id: <8617cb4f27b1f4146b956686f0410e5fc3827379.1612335031.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the file into a DT schema. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 90 +++++++++++++++++++ .../devicetree/bindings/pci/kirin-pcie.txt | 50 ----------- MAINTAINERS | 2 +- 3 files changed, 91 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-p= cie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yam= l b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file mode 100644 index 000000000000..46f9f3f25dbc --- /dev/null +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin SoCs PCIe host DT description + +maintainers: + - Xiaowei Song + - Binghui Wang + +description: | + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. + It shares common functions with the PCIe DesignWare core driver. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# +# - $ref: snps,pcie.yaml# + +properties: + compatible: + const: hisilicon,kirin960-pcie + + reg: + description: | + Should contain rc_dbi, apb, phy, config registers location and lengt= h. + + reg-names: + items: + - const: dbi # controller configuration registers + - const: apb # apb Ctrl register defined by Kirin + - const: phy # apb PHY register defined by Kirin + - const: config # PCIe configuration space registers + + reset-gpios: + description: The GPIO to generate PCIe PERST# assert and deassert sign= al. + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - reset-gpios + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie: pcie@f4000000 { + compatible =3D "hisilicon,kirin960-pcie"; + reg =3D <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xF4000000 0 0x2000>; + reg-names =3D "dbi","apb","phy", "config"; + bus-range =3D <0x0 0x1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges =3D <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000= >; + num-lanes =3D <1>; + #interrupt-cells =3D <1>; + interrupts =3D <0 283 4>; + interrupt-names =3D "msi"; + interrupt-map-mask =3D <0xf800 0 0 7>; + interrupt-map =3D <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names =3D "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", + "pcie_apb_sys", "pcie_aclk"; + reset-gpios =3D <&gpio11 1 0 >; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documen= tation/devicetree/bindings/pci/kirin-pcie.txt deleted file mode 100644 index a38f8e38a67b..000000000000 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ /dev/null @@ -1,50 +0,0 @@ -HiSilicon Kirin SoCs PCIe host DT description - -Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. -It shares common functions with the PCIe DesignWare core driver and -inherits common properties defined in -Documentation/devicetree/bindings/pci/snps,pcie.yaml. - -Additional properties are described here: - -Required properties -- compatible: - "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC -- reg: Should contain rc_dbi, apb, phy, config registers location and leng= th. -- reg-names: Must include the following entries: - "dbi": controller configuration registers; - "apb": apb Ctrl register defined by Kirin; - "phy": apb PHY register defined by Kirin; - "config": PCIe configuration space registers. -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. - -Optional properties: - -Example based on kirin960: - - pcie@f4000000 { - compatible =3D "hisilicon,kirin-pcie"; - reg =3D <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; - reg-names =3D "dbi","apb","phy", "config"; - bus-range =3D <0x0 0x1>; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - ranges =3D <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; - num-lanes =3D <1>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0xf800 0 0 7>; - interrupt-map =3D <0x0 0 0 1 &gic 0 0 0 282 4>, - <0x0 0 0 2 &gic 0 0 0 283 4>, - <0x0 0 0 3 &gic 0 0 0 284 4>, - <0x0 0 0 4 &gic 0 0 0 285 4>; - clocks =3D <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names =3D "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - reset-gpios =3D <&gpio11 1 0 >; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 0bcba0d4994c..701d7115af74 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13817,7 +13817,7 @@ M: Xiaowei Song M: Binghui Wang L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/kirin-pcie.txt +F: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml F: drivers/pci/controller/dwc/pcie-kirin.c =20 PCIE DRIVER FOR HISILICON STB --=20 2.29.2