From nobody Sat May 10 05:43:25 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612272774; cv=none; d=zohomail.com; s=zohoarc; b=E1EzIJnzIE0qUvDZCsa1FgRgHskBsFdAxW09pjdncllQVTs3T7tGE6s0vojWD1140rEIqGPAzkvHa1/zzbYSOlZKcTw43PFk+zcvjRMKI4nCRo2MisckmADpWB+o6pAdR9dMYRBF5ABvzX+1ZX3Gfg+V0HBB6NOsiwvh2aL92Mw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612272774; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YxEYkyPyRL50S1Hp9DhqE3CByWWcFLHzKzq6gQmc3hc=; b=SR950aCBGbh4C0aqrDYh8h9gXdXkt0KusRakUSXYhSTl2q1HL/iWTZWvLtqGUghynLrBjKcgI4cJXSjjskkbyZYp245Wra+/OZbsqcBKmU9LdZ0bPu44HzG+a1+z8eclLpcmxGir+0FwsPpwfRFJpQlLHmKP4saGlqCSt/HoBsE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 1612272774238601.3379986534098; Tue, 2 Feb 2021 05:32:54 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232448AbhBBNcN (ORCPT ); Tue, 2 Feb 2021 08:32:13 -0500 Received: from mail.kernel.org ([198.145.29.99]:59580 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232345AbhBBNb1 (ORCPT ); Tue, 2 Feb 2021 08:31:27 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id DAFFD64EDA; Tue, 2 Feb 2021 13:30:01 +0000 (UTC) Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011zA-S1; Tue, 02 Feb 2021 14:29:59 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=erwwnvc97xuvNb/GIafHSr71dHfEPwM5oq3L6s8voRc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=H9Cb5xpnVcE+fWV4E2SuBYbqZ1Aeb/4PHUCK++GkCu8iRb0oYQMpvUa0c2LzvUF7d eW+cIuEVY6wbjcuNYUI0gZlrWskMit2+jBfUGwTaABlv/97pO0Sf3Kekcs1UQvDAhC 8RLE6790jLzYOQj9NsDALz3qqs6uPeGnZ+LMWIMSZomHhCQ0G6lQNfDco/hq1Je48S HwJxpZBg725ixI8rESo+bOm+gTxKDVvU+bw0tM/zCIll2WB6gkEyTSUV3TFzdN/p7A yWagAEIhd6X1HNvPXCF/bZFNespphPZFNVQ7l3neuIlPJ5U+hf6saEBQtQ2K+3xEPp bKQau2+0EKu8Q== From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 11/13] pci: dwc: pcie-kirin: add support for clkreq GPIOs Date: Tue, 2 Feb 2021 14:29:56 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The PCI hardware on Hikey 970 also need to enable clock lines for PCI bridge, Ethernet and M.2 connector. Those should be enabled during PCI hardware power on logic. Add support for them. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 77 +++++++++++-------------- 1 file changed, 34 insertions(+), 43 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controll= er/dwc/pcie-kirin.c index faf711366309..37b964386d21 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -140,6 +140,8 @@ #define TIME_PHY_PD_MAX 11 =20 #define MAX_GPIO_RESETS 4 +#define MAX_GPIO_CLKREQ 3 + struct kirin_pcie { struct dw_pcie *pci; void __iomem *apb_base; @@ -153,9 +155,11 @@ struct kirin_pcie { struct clk *pcie_aclk; struct clk *pcie_aux_clk; int n_gpio_resets; - int gpio_id_clkreq[3]; + int n_gpio_clkreq; int gpio_id_reset[MAX_GPIO_RESETS]; const char *reset_names[MAX_GPIO_RESETS]; + int gpio_id_clkreq[MAX_GPIO_CLKREQ]; + const char *clkreq_names[MAX_GPIO_CLKREQ]; u32 eye_param[5]; }; =20 @@ -345,6 +349,24 @@ static long kirin_common_pcie_get_resource(struct kiri= n_pcie *kirin_pcie, return -ENOMEM; } =20 + kirin_pcie->n_gpio_clkreq =3D of_gpio_named_count(np, "clkreq-gpios"); + if (kirin_pcie->n_gpio_clkreq > MAX_GPIO_CLKREQ) { + dev_err(dev, "Too many GPIO clock requests!\n"); + return -EINVAL; + } + for (i =3D 0; i < kirin_pcie->n_gpio_clkreq; i++) { + kirin_pcie->gpio_id_clkreq[i] =3D of_get_named_gpio(dev->of_node, + "clkreq-gpios", i); + if (kirin_pcie->gpio_id_clkreq[i] < 0) + return kirin_pcie->gpio_id_clkreq[i]; + + sprintf(name, "pcie_clkreq_%d", i); + kirin_pcie->clkreq_names[i] =3D devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!kirin_pcie->clkreq_names[i]) + return -ENOMEM; + } + return 0; } =20 @@ -360,6 +382,12 @@ static int kirin_gpio_request(struct kirin_pcie *kirin= _pcie, return ret; } =20 + for (i =3D 0; i < kirin_pcie->n_gpio_clkreq; i++) { + ret =3D devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i], + kirin_pcie->clkreq_names[i]); + if (ret) + return ret; + } =20 return ret; } @@ -393,36 +421,6 @@ static long kirin970_pcie_get_resource(struct kirin_pc= ie *kirin_pcie, if (ret) return ret; =20 - kirin_pcie->gpio_id_clkreq[0] =3D of_get_named_gpio(dev->of_node, - "eth,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[0] < 0) - return -ENODEV; - - kirin_pcie->gpio_id_clkreq[1] =3D of_get_named_gpio(dev->of_node, - "m_2,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[1] < 0) - return -ENODEV; - - kirin_pcie->gpio_id_clkreq[2] =3D of_get_named_gpio(dev->of_node, - "mini1,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[2] < 0) - return -ENODEV; - - ret =3D devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[0], - "pcie_eth_clkreq"); - if (ret) - return ret; - - ret =3D devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[1], - "pcie_m_2_clkreq"); - if (ret) - return ret; - - ret =3D devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[2], - "pcie_mini1_clkreq"); - if (ret) - return ret; - kirin_pcie->crgctrl =3D syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl"); if (IS_ERR(kirin_pcie->crgctrl)) @@ -848,7 +846,6 @@ static int kirin970_pcie_noc_power(struct kirin_pcie *k= irin_pcie, bool enable) =20 static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) { - struct device *dev =3D kirin_pcie->pci->dev; int ret, i; u32 val; =20 @@ -858,17 +855,11 @@ static int kirin970_pcie_power_on(struct kirin_pcie *= kirin_pcie) usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); kirin_pcie_oe_enable(kirin_pcie); =20 - ret =3D gpio_direction_output(kirin_pcie->gpio_id_clkreq[0], 0); - if (ret) - dev_err(dev, "Failed to pulse eth clkreq signal\n"); - - ret =3D gpio_direction_output(kirin_pcie->gpio_id_clkreq[1], 0); - if (ret) - dev_err(dev, "Failed to pulse m.2 clkreq signal\n"); - - ret =3D gpio_direction_output(kirin_pcie->gpio_id_clkreq[2], 0); - if (ret) - dev_err(dev, "Failed to pulse mini1 clkreq signal\n"); + for (i =3D 0; i < kirin_pcie->n_gpio_clkreq; i++) { + ret =3D gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0); + if (ret) + return ret; + } =20 ret =3D kirin_pcie_clk_ctrl(kirin_pcie, true); if (ret) --=20 2.29.2