From nobody Sat May 10 05:41:18 2025 Delivered-To: importer2@patchew.org Received-SPF: pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; envelope-from=linux-kernel-owner@vger.kernel.org; helo=vger.kernel.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1612335809; cv=none; d=zohomail.com; s=zohoarc; b=ivn4IRI+XLkcDyX08M8Cwakm+sFGzfmcoDnmF3osmawiV+l9EBtEhe+eD7tq9uA6NiOy65X10T593cU3IaL8ZCwc3n8abfOCsUrQJeUfHHbJpOzN+RU94ErrpbE2QQGBHE3P/3i6BAey5emVBJ1RD4n7INGbw7gZw/1jPNykZcg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612335809; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kHkYv/ktt6BhHZ2zTk1qPdp7zl7EbzIylJ97vYpLDXk=; b=FxWZLX2/50bO/0nA+QHZV0XMaUk1YoVsKdfuHOlsxqzUlSkR88I7qzw3hBPQKDEqSTMLmBOFvO1luOF57RkyS1mLPlGsnshdG70OawR8s0kdrl4/X56/D6GlgSrckZmVCjUP1WZjE7+MlI+qDQXSVTRJsFRIk+EKY1sog61XGZk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mx.zohomail.com with SMTP id 16123358093671009.2808297367158; Tue, 2 Feb 2021 23:03:29 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231913AbhBCHCs (ORCPT ); Wed, 3 Feb 2021 02:02:48 -0500 Received: from mail.kernel.org ([198.145.29.99]:34070 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231717AbhBCHCl (ORCPT ); Wed, 3 Feb 2021 02:02:41 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6ECAD64F65; Wed, 3 Feb 2021 07:02:00 +0000 (UTC) Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l7CAo-001CAl-9W; Wed, 03 Feb 2021 08:01:58 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612335720; bh=XAT5CRmZyM1W+2vKcepEc3Mh6Y6JxLba1gm5DIqVQzI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b51BQW+x2mDzibQWPXp2txL/bv8XIVj+oH4Rz+XR2O+/Id84d2Ex0ZcSWKxBbAUgz VZe9wfwHRNp6LETZoMkS6uw6UgC59rD6N1OpJ73LOD1mPZ/80O/KNnFMZbWpyiPTkA EWyg74VZfXfJokAjrIL4C2d1yzHe4Vgh8ZlrID5nlrela7uMgd4jQEtEzriAtD03/G hsPbJUSAngzPYrSGmbxwavipMAnbKZNRQVhmpQMiFMeabbCJYJ/xXM8niVR0RrfnS5 b8HuJTxll6nkUOyLE1hRLOHjbziw6SOcbMMqxHKHXZjHXJl9pUW2xbmONsidQjDZWr ZGe3wTgcIYQbA== From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 10/11] PCI: dwc: pcie-kirin: add support for clkreq GPIOs Date: Wed, 3 Feb 2021 08:01:54 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The hardware on Kirin 970 designs use external components as part of their PCIe hardware support. Fo instance, in the case of HiKey 970, it has separate clkreq lines that are needed to be enabled on its PCIe bridge, Ethernet chip and even at the M.2 connector hardware. Those should be enabled during PCIe hardware power on logic, as otherwise the resource allocation will fail. Add support for them. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 77 +++++++++++-------------- 1 file changed, 34 insertions(+), 43 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controll= er/dwc/pcie-kirin.c index 4124c6ace349..c5404f1eca28 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -140,6 +140,8 @@ #define TIME_PHY_PD_MAX 11 =20 #define MAX_GPIO_RESETS 4 +#define MAX_GPIO_CLKREQ 3 + struct kirin_pcie { struct dw_pcie *pci; void __iomem *apb_base; @@ -153,9 +155,11 @@ struct kirin_pcie { struct clk *pcie_aclk; struct clk *pcie_aux_clk; int n_gpio_resets; - int gpio_id_clkreq[3]; + int n_gpio_clkreq; int gpio_id_reset[MAX_GPIO_RESETS]; const char *reset_names[MAX_GPIO_RESETS]; + int gpio_id_clkreq[MAX_GPIO_CLKREQ]; + const char *clkreq_names[MAX_GPIO_CLKREQ]; u32 eye_param[5]; }; =20 @@ -345,6 +349,24 @@ static long kirin_common_pcie_get_resource(struct kiri= n_pcie *kirin_pcie, return -ENOMEM; } =20 + kirin_pcie->n_gpio_clkreq =3D of_gpio_named_count(np, "clkreq-gpios"); + if (kirin_pcie->n_gpio_clkreq > MAX_GPIO_CLKREQ) { + dev_err(dev, "Too many GPIO clock requests!\n"); + return -EINVAL; + } + for (i =3D 0; i < kirin_pcie->n_gpio_clkreq; i++) { + kirin_pcie->gpio_id_clkreq[i] =3D of_get_named_gpio(dev->of_node, + "clkreq-gpios", i); + if (kirin_pcie->gpio_id_clkreq[i] < 0) + return kirin_pcie->gpio_id_clkreq[i]; + + sprintf(name, "pcie_clkreq_%d", i); + kirin_pcie->clkreq_names[i] =3D devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!kirin_pcie->clkreq_names[i]) + return -ENOMEM; + } + return 0; } =20 @@ -360,6 +382,12 @@ static int kirin_gpio_request(struct kirin_pcie *kirin= _pcie, return ret; } =20 + for (i =3D 0; i < kirin_pcie->n_gpio_clkreq; i++) { + ret =3D devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i], + kirin_pcie->clkreq_names[i]); + if (ret) + return ret; + } =20 return ret; } @@ -406,36 +434,6 @@ static long kirin970_pcie_get_resource(struct kirin_pc= ie *kirin_pcie, if (ret) return ret; =20 - kirin_pcie->gpio_id_clkreq[0] =3D of_get_named_gpio(dev->of_node, - "eth,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[0] < 0) - return -ENODEV; - - kirin_pcie->gpio_id_clkreq[1] =3D of_get_named_gpio(dev->of_node, - "m_2,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[1] < 0) - return -ENODEV; - - kirin_pcie->gpio_id_clkreq[2] =3D of_get_named_gpio(dev->of_node, - "mini1,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[2] < 0) - return -ENODEV; - - ret =3D devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[0], - "pcie_eth_clkreq"); - if (ret) - return ret; - - ret =3D devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[1], - "pcie_m_2_clkreq"); - if (ret) - return ret; - - ret =3D devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[2], - "pcie_mini1_clkreq"); - if (ret) - return ret; - kirin_pcie->crgctrl =3D syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl"); if (IS_ERR(kirin_pcie->crgctrl)) @@ -861,7 +859,6 @@ static int kirin970_pcie_noc_power(struct kirin_pcie *k= irin_pcie, bool enable) =20 static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) { - struct device *dev =3D kirin_pcie->pci->dev; int ret, i; u32 val; =20 @@ -871,17 +868,11 @@ static int kirin970_pcie_power_on(struct kirin_pcie *= kirin_pcie) usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); kirin_pcie_oe_enable(kirin_pcie); =20 - ret =3D gpio_direction_output(kirin_pcie->gpio_id_clkreq[0], 0); - if (ret) - dev_err(dev, "Failed to pulse eth clkreq signal\n"); - - ret =3D gpio_direction_output(kirin_pcie->gpio_id_clkreq[1], 0); - if (ret) - dev_err(dev, "Failed to pulse m.2 clkreq signal\n"); - - ret =3D gpio_direction_output(kirin_pcie->gpio_id_clkreq[2], 0); - if (ret) - dev_err(dev, "Failed to pulse mini1 clkreq signal\n"); + for (i =3D 0; i < kirin_pcie->n_gpio_clkreq; i++) { + ret =3D gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0); + if (ret) + return ret; + } =20 ret =3D kirin_pcie_clk_ctrl(kirin_pcie, true); if (ret) --=20 2.29.2