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[edk2] [PATCH v3 3/5] UefiCpuPkg/PiSmmCpuDxeSmm: Use FixedPCDs to enhance SMM support

Leo Duran posted 5 patches 7 years, 2 months ago
There is a newer version of this series
[edk2] [PATCH v3 3/5] UefiCpuPkg/PiSmmCpuDxeSmm: Use FixedPCDs to enhance SMM support
Posted by Leo Duran 7 years, 2 months ago 
Consume a couple of FixedPCDs to replace Intel-specific macros.
The new PCDs will allow SMM support on AMD-based x86 systems.

1) PcdCpuSmmSmramSaveStateMapOffset - SMRAM Save State Map Offset.
2) PcdCpuSmmPSDOffset - Processor SMM Descriptor Offset in SMRAM.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c         |  4 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S          |  4 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm        |  4 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm       |  4 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c         | 10 +++++-----
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h         |  2 --
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c |  4 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c         |  4 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c          |  4 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S           |  4 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm         |  4 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm        |  4 +++-
 12 files changed, 35 insertions(+), 17 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c
index 02a866b..cc2624e 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c
@@ -3,6 +3,8 @@ Semaphore mechanism to indicate to the BSP that an AP has exited SMM
 after SMBASE relocation.
 
 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
 which accompanies this distribution.  The full text of the license may be found at
@@ -38,7 +40,7 @@ SemaphoreHook (
 
   mRebasedFlag = RebasedFlag;
 
-  CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+  CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset));
   mSmmRelocationOriginalAddress = (UINTN)HookReturnFromSmm (
                                            CpuIndex,
                                            CpuState,
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
index 3243a91..25af6e7 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
@@ -1,6 +1,8 @@
 #------------------------------------------------------------------------------
 #
 # Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+#
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License
 # which accompanies this distribution.  The full text of the license may be found at
@@ -35,7 +37,7 @@ ASM_GLOBAL  ASM_PFX(gSmiHandlerIdtr)
 #
 # Constants relating to PROCESSOR_SMM_DESCRIPTOR
 #
-.equ            DSC_OFFSET, 0xfb00
+.equ            DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset))
 .equ            DSC_GDTPTR, 0x30
 .equ            DSC_GDTSIZ, 0x38
 .equ            DSC_CS, 14
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
index 8296f36..f526778 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
@@ -1,5 +1,7 @@
 ;------------------------------------------------------------------------------ ;
 ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
 ; This program and the accompanying materials
 ; are licensed and made available under the terms and conditions of the BSD License
 ; which accompanies this distribution.  The full text of the license may be found at
@@ -29,7 +31,7 @@ MSR_EFER_XD   EQU     0800h
 ;
 ; Constants relating to PROCESSOR_SMM_DESCRIPTOR
 ;
-DSC_OFFSET    EQU     0fb00h
+DSC_OFFSET    EQU     (FixedPcdGet16 (PcdCpuSmmPSDOffset))
 DSC_GDTPTR    EQU     30h
 DSC_GDTSIZ    EQU     38h
 DSC_CS        EQU     14
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 4d2383f..9092dcc 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -1,5 +1,7 @@
 ;------------------------------------------------------------------------------ ;
 ; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
 ; This program and the accompanying materials
 ; are licensed and made available under the terms and conditions of the BSD License
 ; which accompanies this distribution.  The full text of the license may be found at
@@ -25,7 +27,7 @@
 ;
 ; Constants relating to PROCESSOR_SMM_DESCRIPTOR
 ;
-%define DSC_OFFSET 0xfb00
+%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset))
 %define DSC_GDTPTR 0x30
 %define DSC_GDTSIZ 0x38
 %define DSC_CS 14
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 282d2e6..b2a941e 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -407,7 +407,7 @@ SmmRelocateBases (
   gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;
 
   U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);
-  CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+  CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset));
 
   //
   // Backup original contents at address 0x38000
@@ -707,12 +707,12 @@ PiCpuSmmEntry (
 
   //
   // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
-  // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.
+  // specific context start starts at SMBASE + PcdCpuSmmPSDOffset, and the SMI entry point.
   // This size is rounded up to nearest power of 2.
   //
   TileCodeSize = GetSmiHandlerSize ();
   TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
-  TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
+  TileDataSize = (FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset) - FixedPcdGet16 (PcdCpuSmmPSDOffset)) + sizeof (SMRAM_SAVE_STATE_MAP);
   TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
   TileSize = TileDataSize + TileCodeSize - 1;
   TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
@@ -725,7 +725,7 @@ PiCpuSmmEntry (
   // the SMI Handler size must be reduced or the size of the extra CPU specific
   // context must be reduced.
   //
-  ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));
+  ASSERT (TileSize <= (FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset) + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));
 
   //
   // Allocate buffer for all of the tiles.
@@ -783,7 +783,7 @@ PiCpuSmmEntry (
   for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
     mCpuHotPlugData.SmBase[Index]          = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;
     gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP);
-    gSmmCpuPrivate->CpuSaveState[Index]     = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);
+    gSmmCpuPrivate->CpuSaveState[Index]     = (VOID *)(mCpuHotPlugData.SmBase[Index] + FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset));
     gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
 
     if (Index < mNumberOfCpus) {
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 1cf85c1..31e4f53 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -360,8 +360,6 @@ typedef struct {
   UINT32       MsrIndex;
 } MP_MSR_LOCK;
 
-#define SMM_PSD_OFFSET              0xfb00
-
 ///
 /// All global semaphores' pointer
 ///
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index 3ad5256..147b694 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -1,6 +1,8 @@
 /** @file
 
 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
 which accompanies this distribution.  The full text of the license may be found at
@@ -703,7 +705,7 @@ PatchSmmSaveStateMap (
 
   TileCodeSize = GetSmiHandlerSize ();
   TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
-  TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
+  TileDataSize = (FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset) - FixedPcdGet16 (PcdCpuSmmPSDOffset)) + sizeof (SMRAM_SAVE_STATE_MAP);
   TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
   TileSize = TileDataSize + TileCodeSize - 1;
   TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
index 3188d43..d59b9a0 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -2,6 +2,8 @@
 Provides services to access SMRAM Save State Map
 
 Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
 which accompanies this distribution.  The full text of the license may be found at
@@ -690,7 +692,7 @@ InstallSmiHandler (
   //
   // Initialize PROCESSOR_SMM_DESCRIPTOR
   //
-  Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFFSET);
+  Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + FixedPcdGet16 (PcdCpuSmmPSDOffset));
   CopyMem (Psd, &gcPsd, sizeof (gcPsd));
   Psd->SmmGdtPtr = (UINT64)GdtBase;
   Psd->SmmGdtSize = (UINT32)GdtSize;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
index 6dbcb08..e74bb69 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
@@ -3,6 +3,8 @@ Semaphore mechanism to indicate to the BSP that an AP has exited SMM
 after SMBASE relocation.
 
 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
 which accompanies this distribution.  The full text of the license may be found at
@@ -51,7 +53,7 @@ SemaphoreHook (
   mRebasedFlag       = RebasedFlag;
   mRebasedFlagAddr32 = (UINT32)(UINTN)mRebasedFlag;
 
-  CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+  CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + FixedPcdGet16 (PcdCpuSmmSmramSaveStateMapOffset));
   mSmmRelocationOriginalAddress = HookReturnFromSmm (
                                     CpuIndex,
                                     CpuState,
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
index 600d862..ebea477 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
@@ -1,6 +1,8 @@
 #------------------------------------------------------------------------------
 #
 # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+#
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License
 # which accompanies this distribution.  The full text of the license may be found at
@@ -34,7 +36,7 @@ ASM_GLOBAL  ASM_PFX(gSmiHandlerIdtr)
 #
 # Constants relating to PROCESSOR_SMM_DESCRIPTOR
 #
-.equ            DSC_OFFSET, 0xfb00
+.equ            DSC_OFFSET, (FixedPcdGet16 (PcdCpuSmmPSDOffset))
 .equ            DSC_GDTPTR, 0x30
 .equ            DSC_GDTSIZ, 0x38
 .equ            DSC_CS, 14
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
index c74f82a..ff46838 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
@@ -1,5 +1,7 @@
 ;------------------------------------------------------------------------------ ;
 ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
 ; This program and the accompanying materials
 ; are licensed and made available under the terms and conditions of the BSD License
 ; which accompanies this distribution.  The full text of the license may be found at
@@ -39,7 +41,7 @@ MSR_EFER_XD   EQU     0800h
 ;
 ; Constants relating to PROCESSOR_SMM_DESCRIPTOR
 ;
-DSC_OFFSET    EQU     0fb00h
+DSC_OFFSET    EQU     (FixedPcdGet16 (PcdCpuSmmPSDOffset))
 DSC_GDTPTR    EQU     30h
 DSC_GDTSIZ    EQU     38h
 DSC_CS        EQU     14
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index c3c094f..f55da9b 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -1,5 +1,7 @@
 ;------------------------------------------------------------------------------ ;
 ; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
 ; This program and the accompanying materials
 ; are licensed and made available under the terms and conditions of the BSD License
 ; which accompanies this distribution.  The full text of the license may be found at
@@ -29,7 +31,7 @@
 ;
 ; Constants relating to PROCESSOR_SMM_DESCRIPTOR
 ;
-%define DSC_OFFSET 0xfb00
+%define DSC_OFFSET (FixedPcdGet16 (PcdCpuSmmPSDOffset))
 %define DSC_GDTPTR 0x30
 %define DSC_GDTSIZ 0x38
 %define DSC_CS 14
-- 
2.7.4

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