From: Evan Wang <xswang@marvell.com>
PCIE clock direction (input/output) has implications on comphy settings.
There are 2 PCIe clocks in CP110:
- Ref clock 0 for lanes 1,2 and 3
- Ref clock 1 for lanes 4 and 5
A proper handling of above had to be added, using newly introduced
sample at reset library class for Marvell SoCs.
Other than that, update HPIPE settings and the reset sequence,
which differ from one used in x1 link.
This patch fixes PCIE x4 and x2 configuration, which helps
to overcome link establishing issue for multi-lane end points.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Evan Wang <xswang@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 +
Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 216 +++++++++++++++-----
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 1 +
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 20 ++
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 +
5 files changed, 187 insertions(+), 52 deletions(-)
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index ef70b52..bb2ec6c 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -35,6 +35,7 @@
ArmPlatformLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
MppLib|Silicon/Marvell/Library/MppLib/MppLib.inf
+ MvSARLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Armada7k8kSARLib.inf
NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf
UtmiPhyLib|Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 40a7b99..25b8b7c 100755
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -34,6 +34,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include "ComPhyLib.h"
#include <Library/MvHwDescLib.h>
+#include <Library/MvSARLib.h>
#define SD_LANE_ADDR_WIDTH 0x1000
#define HPIPE_ADDR_OFFSET 0x800
@@ -42,6 +43,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)
#define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane)
+#define CP110_PCIE_REF_CLK_TYPE0 0
+#define CP110_PCIE_REF_CLK_TYPE12 1
+
DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;
/*
@@ -99,11 +103,26 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
STATIC
VOID
ComPhyPcieRFUConfiguration (
+ IN UINT32 Lane,
+ IN UINT32 PcieWidth,
IN EFI_PHYSICAL_ADDRESS ComPhyAddr
)
{
UINT32 Mask, Data;
+ /* Enable PCIe by4 and by2 */
+ if (Lane == 0) {
+ if (PcieWidth == 4) {
+ RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
+ 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET,
+ COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
+ } else if (PcieWidth == 2) {
+ RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
+ 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET,
+ COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
+ }
+ }
+
/* RFU configurations - hard reset ComPhy */
Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
@@ -132,11 +151,14 @@ ComPhyPcieRFUConfiguration (
STATIC
VOID
ComPhyPciePhyConfiguration (
+ IN UINT32 Lane,
+ IN UINT32 PcieWidth,
+ IN UINT32 PcieClk,
IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
IN EFI_PHYSICAL_ADDRESS HpipeAddr
)
{
- UINT32 Mask, Data, PcieClk = 0;
+ UINT32 Mask, Data;
/* Set PIPE soft reset */
Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
@@ -156,13 +178,31 @@ ComPhyPciePhyConfiguration (
RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask);
/* Set PLL ready delay for 0x2 */
- RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG,
- 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
- HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
+ Data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET;
+ Mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
+ if (PcieWidth != 1) {
+ Data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET |
+ 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET;
+ Mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK |
+ HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
+ }
+ RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, Data, Mask);
/* Set PIPE mode interface to PCIe3 - 0x1 */
- RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG,
- 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET, HPIPE_CLK_SRC_HI_MODE_PIPE_MASK);
+ Data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET;
+ Mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
+ if (PcieWidth != 1) {
+ Mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK |
+ HPIPE_CLK_SRC_HI_LANE_MASTER_MASK |
+ HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
+ if (Lane == 0) {
+ Data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET |
+ 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET;
+ } else if (Lane == (PcieWidth - 1)) {
+ Data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET;
+ }
+ }
+ RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, Data, Mask);
/* Config update polarity equalization */
RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG,
@@ -172,19 +212,21 @@ ComPhyPciePhyConfiguration (
RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG,
0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK);
- /* Enable PIN clock 100M_125M */
- Mask = HPIPE_MISC_CLK100M_125M_MASK;
- Data = 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
-
/* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */
- Mask |= HPIPE_MISC_TXDCLK_2X_MASK;
- Data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
+ Mask = HPIPE_MISC_TXDCLK_2X_MASK;
+ Data = 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
/* Enable 500MHz Clock */
Mask |= HPIPE_MISC_CLK500_EN_MASK;
Data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
if (PcieClk) {
+ /*
+ * Enable PIN clock 100M_125M
+ * Only if clock is output, configure the clock-source mux
+ */
+ Mask |= HPIPE_MISC_CLK100M_125M_MASK;
+ Data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
/* Set reference clock comes from group 1 */
Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
Data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
@@ -214,6 +256,13 @@ ComPhyPciePhyConfiguration (
Data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
+ /* Ref clock alignment */
+ if (PcieWidth != 1) {
+ RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG,
+ 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET,
+ HPIPE_LANE_ALIGN_OFF_MASK);
+ }
+
/*
* Set the amount of time spent in the LoZ state - set
* for 0x7 only if the PCIe clock is output
@@ -404,37 +453,86 @@ ComPhyPcieSetAnalogParameters (
}
STATIC
-VOID
-ComPhyPciePhyPowerUp (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr
-)
-{
- /* Release from PIPE soft reset */
- RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG,
- 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
- HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
-
- /* Wait 15ms - for ComPhy calibration done */
- MicroSecondDelay (15000);
- MemoryFence ();
-}
-
-STATIC
EFI_STATUS
-ComPhyPcieCheckPll (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr
+ComPhyPciePhyPowerUp (
+ IN UINT32 Lane,
+ IN UINT32 PcieWidth,
+ IN EFI_PHYSICAL_ADDRESS ComPhyBase,
+ IN EFI_PHYSICAL_ADDRESS HpipeBase
)
{
EFI_STATUS Status = EFI_SUCCESS;
- UINT32 Data;
+ UINT8 StartLane, EndLane, Loop;
+ UINT32 Data, UsecTimout;
- /* Read Lane status */
- Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG);
- if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
- DEBUG((DEBUG_INFO, "ComPhy: Read from reg = %p - value = 0x%x\n",
- HpipeAddr + HPIPE_LANE_STATUS0_REG, Data));
- DEBUG((DEBUG_INFO, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n"));
- Status = EFI_D_ERROR;
+ /*
+ * For PCIe by4 or by2 - release from reset only after finish to
+ * configure all lanes
+ */
+ if ((PcieWidth == 1) || (Lane == (PcieWidth - 1))) {
+ if (PcieWidth != 1) {
+ /* Allows writing to all lanes in one write */
+ RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
+ 0x0 << COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
+ COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
+ StartLane = 0;
+ EndLane = PcieWidth;
+
+ /*
+ * Release from PIPE soft reset
+ * for PCIe by4 or by2 - release from soft reset
+ * all lanes - can't use read modify write
+ */
+ RegSet (HPIPE_ADDR (HpipeBase, 0) + HPIPE_RST_CLK_CTRL_REG,
+ HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 | HPIPE_RST_CLK_CTRL_MODE_REFDIV_4,
+ HPIPE_RST_CLK_CTRL_CLR_ALL_MASK);
+ } else {
+ StartLane = Lane;
+ EndLane = Lane + 1;
+
+ /*
+ * Release from PIPE soft reset
+ * for PCIe by4 or by2 - release from soft reset
+ * all lanes
+ */
+ RegSet (HPIPE_ADDR (HpipeBase, Lane) + HPIPE_RST_CLK_CTRL_REG,
+ 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
+ HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
+ }
+
+ if (PcieWidth != 1) {
+ /* Disable writing to all lanes with one write */
+ RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
+ 0x3210 << COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
+ COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
+ }
+ MemoryFence ();
+
+ /* Read lane status */
+ for (Loop = StartLane; Loop < EndLane; Loop++) {
+ Data = 0;
+ UsecTimout = 15000;
+
+ do {
+ MicroSecondDelay (1);
+ Data = MmioRead32 (HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG);
+ Data &= HPIPE_LANE_STATUS0_PCLK_EN_MASK;
+ } while (Data == 0 && --UsecTimout > 0);
+
+ if (UsecTimout == 0 && Data == 0) {
+ DEBUG ((DEBUG_ERROR,
+ "%a: Read from lane%d, reg = %p - value = 0x%x\n",
+ __FUNCTION__,
+ Loop,
+ HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG,
+ Data));
+ DEBUG ((DEBUG_ERROR,
+ "%a: HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n",
+ __FUNCTION__));
+ Status = EFI_D_ERROR;
+ break;
+ }
+ }
}
return Status;
@@ -443,8 +541,9 @@ ComPhyPcieCheckPll (
STATIC
EFI_STATUS
ComPhyPciePowerUp (
+ IN UINT8 ChipId,
IN UINT32 Lane,
- IN UINT32 PcieBy4,
+ IN UINT32 PcieWidth,
IN EFI_PHYSICAL_ADDRESS HpipeBase,
IN EFI_PHYSICAL_ADDRESS ComPhyBase
)
@@ -452,26 +551,32 @@ ComPhyPciePowerUp (
EFI_STATUS Status = EFI_SUCCESS;
EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
+ UINT32 PcieClk;
+
+ /* Lane4 and 5 only for PCIe port 1 and 2 */
+ if (Lane == 4 || Lane == 5) {
+ PcieClk = MvSARGetPcieClkDirection (ChipId, CP110_PCIE_REF_CLK_TYPE12);
+ } else {
+ PcieClk = MvSARGetPcieClkDirection (ChipId, CP110_PCIE_REF_CLK_TYPE0);
+ }
+
+ DEBUG ((DEBUG_INFO, "%a: ChipId: %d PcieClk:%d\n", __FUNCTION__, ChipId, PcieClk));
DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
- ComPhyPcieRFUConfiguration (ComPhyAddr);
+ ComPhyPcieRFUConfiguration (Lane, PcieWidth, ComPhyAddr);
DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
- ComPhyPciePhyConfiguration (ComPhyAddr, HpipeAddr);
+ ComPhyPciePhyConfiguration (Lane, PcieWidth, PcieClk, ComPhyAddr, HpipeAddr);
DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
ComPhyPcieSetAnalogParameters (HpipeAddr);
- DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));
+ DEBUG ((DEBUG_INFO, "%a: stage: ComPhy power up and check PLL\n", __FUNCTION__));
- ComPhyPciePhyPowerUp (HpipeAddr);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));
-
- Status = ComPhyPcieCheckPll (HpipeAddr);
+ Status = ComPhyPciePhyPowerUp (Lane, PcieWidth, ComPhyBase, HpipeBase);
return Status;
}
@@ -1780,28 +1885,35 @@ ComPhyCp110Init (
COMPHY_MAP *PtrComPhyMap, *SerdesMap;
EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr;
UINT32 ComPhyMaxCount, Lane;
- UINT32 PcieBy4 = 1; // Indicating if first 4 lanes set to PCIE
+ UINT32 PcieWidth = 0;
+ UINT8 ChipId;
ComPhyMaxCount = PtrChipCfg->LanesCount;
ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr;
HpipeBaseAddr = PtrChipCfg->Hpipe3BaseAddr;
SerdesMap = PtrChipCfg->MapData;
+ ChipId = PtrChipCfg->ChipId;
/* Config Comphy mux configuration */
ComPhyMuxCp110(PtrChipCfg, SerdesMap);
/* Check if the first 4 Lanes configured as By-4 */
for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++, PtrComPhyMap++) {
- if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0) {
- PcieBy4 = 0;
+ if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0)
break;
- }
+ PcieWidth++;
}
for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < ComPhyMaxCount;
Lane++, PtrComPhyMap++) {
DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane));
DEBUG((DEBUG_INFO, "ComPhy: Serdes Type = 0x%x\n", PtrComPhyMap->Type));
+
+ if (Lane >= 4) {
+ /* PCIe lanes above the first 4 lanes, can be only by1 */
+ PcieWidth = 1;
+ }
+
switch (PtrComPhyMap->Type) {
case COMPHY_TYPE_UNCONNECTED:
continue;
@@ -1810,7 +1922,7 @@ ComPhyCp110Init (
case COMPHY_TYPE_PCIE1:
case COMPHY_TYPE_PCIE2:
case COMPHY_TYPE_PCIE3:
- Status = ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr, ComPhyBaseAddr);
+ Status = ComPhyPciePowerUp (ChipId, Lane, PcieWidth, HpipeBaseAddr, ComPhyBaseAddr);
break;
case COMPHY_TYPE_SATA0:
case COMPHY_TYPE_SATA1:
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
index bf21dca..b03bc35 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
@@ -192,6 +192,7 @@ InitComPhyConfig (
ChipConfig->Hpipe3BaseAddr = Desc->ComPhyHpipe3BaseAddresses[Id];
ChipConfig->LanesCount = Desc->ComPhyLaneCount[Id];
ChipConfig->MuxBitCount = Desc->ComPhyMuxBitCount[Id];
+ ChipConfig->ChipId = Id;
/*
* Below macro contains variable name concatenation (used to form PCD's name).
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
index 5899a4a..710ec80 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
@@ -479,16 +479,29 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
#define HPIPE_RST_CLK_CTRL_REG 0x704
+#define HPIPE_RST_CLK_CTRL_CLR_ALL_MASK 0xffffffff
#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
+#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
+#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_16 (0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET 4
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_MASK (0x3 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_1 (0x0 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_2 (0x1 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_4 (0x2 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_8 (0x3 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
#define HPIPE_CLK_SRC_LO_REG 0x70c
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
@@ -528,6 +541,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define COMMON_SELECTOR_PIPE_OFFSET 0x144
#define COMMON_PHY_SD_CTRL1 0x148
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
+#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
+#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
+#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
+#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
@@ -594,6 +613,7 @@ struct _CHIP_COMPHY_CONFIG {
COMPHY_CHIP_INIT Init;
UINT32 LanesCount;
UINT32 MuxBitCount;
+ UINT8 ChipId;
};
VOID
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
index a1584b4..f00180c 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
@@ -49,6 +49,7 @@
ArmLib
DebugLib
MemoryAllocationLib
+ MvSARLib
PcdLib
IoLib
--
2.7.4
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
On Fri, Feb 16, 2018 at 05:35:27PM +0100, Marcin Wojtas wrote:
> From: Evan Wang <xswang@marvell.com>
>
> PCIE clock direction (input/output) has implications on comphy settings.
> There are 2 PCIe clocks in CP110:
> - Ref clock 0 for lanes 1,2 and 3
> - Ref clock 1 for lanes 4 and 5
> A proper handling of above had to be added, using newly introduced
> sample at reset library class for Marvell SoCs.
>
> Other than that, update HPIPE settings and the reset sequence,
> which differ from one used in x1 link.
>
> This patch fixes PCIE x4 and x2 configuration, which helps
> to overcome link establishing issue for multi-lane end points.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Evan Wang <xswang@marvell.com>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 +
> Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 216 +++++++++++++++-----
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 1 +
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 20 ++
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 +
> 5 files changed, 187 insertions(+), 52 deletions(-)
>
> diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> index ef70b52..bb2ec6c 100644
> --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> @@ -35,6 +35,7 @@
> ArmPlatformLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
> ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> MppLib|Silicon/Marvell/Library/MppLib/MppLib.inf
> + MvSARLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSARLib/Armada7k8kSARLib.inf
> NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf
> UtmiPhyLib|Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf
>
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> index 40a7b99..25b8b7c 100755
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> @@ -34,6 +34,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>
> #include "ComPhyLib.h"
> #include <Library/MvHwDescLib.h>
> +#include <Library/MvSARLib.h>
>
> #define SD_LANE_ADDR_WIDTH 0x1000
> #define HPIPE_ADDR_OFFSET 0x800
> @@ -42,6 +43,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> #define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)
> #define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane)
>
> +#define CP110_PCIE_REF_CLK_TYPE0 0
> +#define CP110_PCIE_REF_CLK_TYPE12 1
> +
> DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;
>
> /*
> @@ -99,11 +103,26 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
> STATIC
> VOID
> ComPhyPcieRFUConfiguration (
> + IN UINT32 Lane,
> + IN UINT32 PcieWidth,
> IN EFI_PHYSICAL_ADDRESS ComPhyAddr
> )
> {
> UINT32 Mask, Data;
>
> + /* Enable PCIe by4 and by2 */
> + if (Lane == 0) {
> + if (PcieWidth == 4) {
> + RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
> + 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET,
I don't object to _having_ _OFFSET definitions, but to expand them on
each use is just noisy.
Please (for all of these) add something like
#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
> + COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
> + } else if (PcieWidth == 2) {
> + RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
> + 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET,
> + COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
> + }
> + }
> +
> /* RFU configurations - hard reset ComPhy */
> Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
> Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
> @@ -132,11 +151,14 @@ ComPhyPcieRFUConfiguration (
> STATIC
> VOID
> ComPhyPciePhyConfiguration (
> + IN UINT32 Lane,
> + IN UINT32 PcieWidth,
> + IN UINT32 PcieClk,
> IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
> IN EFI_PHYSICAL_ADDRESS HpipeAddr
> )
> {
> - UINT32 Mask, Data, PcieClk = 0;
> + UINT32 Mask, Data;
>
> /* Set PIPE soft reset */
> Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
> @@ -156,13 +178,31 @@ ComPhyPciePhyConfiguration (
> RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask);
>
> /* Set PLL ready delay for 0x2 */
> - RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG,
> - 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
> - HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
> + Data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET;
> + Mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
> + if (PcieWidth != 1) {
> + Data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET |
> + 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET;
> + Mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK |
> + HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
> + }
> + RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, Data, Mask);
>
> /* Set PIPE mode interface to PCIe3 - 0x1 */
> - RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG,
> - 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET, HPIPE_CLK_SRC_HI_MODE_PIPE_MASK);
> + Data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET;
> + Mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
> + if (PcieWidth != 1) {
> + Mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK |
> + HPIPE_CLK_SRC_HI_LANE_MASTER_MASK |
> + HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
> + if (Lane == 0) {
> + Data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET |
> + 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET;
> + } else if (Lane == (PcieWidth - 1)) {
> + Data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET;
> + }
> + }
> + RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, Data, Mask);
>
> /* Config update polarity equalization */
> RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG,
> @@ -172,19 +212,21 @@ ComPhyPciePhyConfiguration (
> RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG,
> 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK);
>
> - /* Enable PIN clock 100M_125M */
> - Mask = HPIPE_MISC_CLK100M_125M_MASK;
> - Data = 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
> -
> /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */
> - Mask |= HPIPE_MISC_TXDCLK_2X_MASK;
> - Data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
> + Mask = HPIPE_MISC_TXDCLK_2X_MASK;
> + Data = 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
>
> /* Enable 500MHz Clock */
> Mask |= HPIPE_MISC_CLK500_EN_MASK;
> Data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
>
> if (PcieClk) {
> + /*
> + * Enable PIN clock 100M_125M
> + * Only if clock is output, configure the clock-source mux
> + */
> + Mask |= HPIPE_MISC_CLK100M_125M_MASK;
> + Data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
> /* Set reference clock comes from group 1 */
> Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
> Data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
> @@ -214,6 +256,13 @@ ComPhyPciePhyConfiguration (
> Data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
> RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
>
> + /* Ref clock alignment */
> + if (PcieWidth != 1) {
> + RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG,
> + 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET,
> + HPIPE_LANE_ALIGN_OFF_MASK);
> + }
> +
> /*
> * Set the amount of time spent in the LoZ state - set
> * for 0x7 only if the PCIe clock is output
> @@ -404,37 +453,86 @@ ComPhyPcieSetAnalogParameters (
> }
>
> STATIC
> -VOID
> -ComPhyPciePhyPowerUp (
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr
> -)
> -{
> - /* Release from PIPE soft reset */
> - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG,
> - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
> - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
> -
> - /* Wait 15ms - for ComPhy calibration done */
> - MicroSecondDelay (15000);
> - MemoryFence ();
> -}
> -
> -STATIC
> EFI_STATUS
> -ComPhyPcieCheckPll (
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr
> +ComPhyPciePhyPowerUp (
> + IN UINT32 Lane,
> + IN UINT32 PcieWidth,
> + IN EFI_PHYSICAL_ADDRESS ComPhyBase,
> + IN EFI_PHYSICAL_ADDRESS HpipeBase
> )
> {
> EFI_STATUS Status = EFI_SUCCESS;
> - UINT32 Data;
> + UINT8 StartLane, EndLane, Loop;
> + UINT32 Data, UsecTimout;
>
> - /* Read Lane status */
> - Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG);
> - if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
> - DEBUG((DEBUG_INFO, "ComPhy: Read from reg = %p - value = 0x%x\n",
> - HpipeAddr + HPIPE_LANE_STATUS0_REG, Data));
> - DEBUG((DEBUG_INFO, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n"));
> - Status = EFI_D_ERROR;
> + /*
> + * For PCIe by4 or by2 - release from reset only after finish to
> + * configure all lanes
> + */
> + if ((PcieWidth == 1) || (Lane == (PcieWidth - 1))) {
> + if (PcieWidth != 1) {
> + /* Allows writing to all lanes in one write */
> + RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
> + 0x0 << COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
> + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
> + StartLane = 0;
> + EndLane = PcieWidth;
> +
> + /*
> + * Release from PIPE soft reset
> + * for PCIe by4 or by2 - release from soft reset
> + * all lanes - can't use read modify write
> + */
> + RegSet (HPIPE_ADDR (HpipeBase, 0) + HPIPE_RST_CLK_CTRL_REG,
> + HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 | HPIPE_RST_CLK_CTRL_MODE_REFDIV_4,
> + HPIPE_RST_CLK_CTRL_CLR_ALL_MASK);
> + } else {
> + StartLane = Lane;
> + EndLane = Lane + 1;
> +
> + /*
> + * Release from PIPE soft reset
> + * for PCIe by4 or by2 - release from soft reset
> + * all lanes
> + */
> + RegSet (HPIPE_ADDR (HpipeBase, Lane) + HPIPE_RST_CLK_CTRL_REG,
> + 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
> + HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
> + }
> +
> + if (PcieWidth != 1) {
> + /* Disable writing to all lanes with one write */
> + RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
> + 0x3210 << COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
No live coding. Add a suitable #define.
> + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
> + }
> + MemoryFence ();
> +
> + /* Read lane status */
> + for (Loop = StartLane; Loop < EndLane; Loop++) {
> + Data = 0;
> + UsecTimout = 15000;
Why 15000?
> +
> + do {
> + MicroSecondDelay (1);
> + Data = MmioRead32 (HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG);
> + Data &= HPIPE_LANE_STATUS0_PCLK_EN_MASK;
> + } while (Data == 0 && --UsecTimout > 0);
> +
> + if (UsecTimout == 0 && Data == 0) {
> + DEBUG ((DEBUG_ERROR,
> + "%a: Read from lane%d, reg = %p - value = 0x%x\n",
> + __FUNCTION__,
> + Loop,
> + HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG,
> + Data));
> + DEBUG ((DEBUG_ERROR,
> + "%a: HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n",
> + __FUNCTION__));
> + Status = EFI_D_ERROR;
> + break;
> + }
> + }
> }
>
> return Status;
> @@ -443,8 +541,9 @@ ComPhyPcieCheckPll (
> STATIC
> EFI_STATUS
> ComPhyPciePowerUp (
> + IN UINT8 ChipId,
> IN UINT32 Lane,
> - IN UINT32 PcieBy4,
> + IN UINT32 PcieWidth,
> IN EFI_PHYSICAL_ADDRESS HpipeBase,
> IN EFI_PHYSICAL_ADDRESS ComPhyBase
> )
> @@ -452,26 +551,32 @@ ComPhyPciePowerUp (
> EFI_STATUS Status = EFI_SUCCESS;
> EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
> EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
> + UINT32 PcieClk;
> +
> + /* Lane4 and 5 only for PCIe port 1 and 2 */
What does this mean?
I need to uinderstand this comment without reaching for the TRM.
> + if (Lane == 4 || Lane == 5) {
> + PcieClk = MvSARGetPcieClkDirection (ChipId, CP110_PCIE_REF_CLK_TYPE12);
> + } else {
> + PcieClk = MvSARGetPcieClkDirection (ChipId, CP110_PCIE_REF_CLK_TYPE0);
> + }
> +
> + DEBUG ((DEBUG_INFO, "%a: ChipId: %d PcieClk:%d\n", __FUNCTION__, ChipId, PcieClk));
>
> DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
>
> - ComPhyPcieRFUConfiguration (ComPhyAddr);
> + ComPhyPcieRFUConfiguration (Lane, PcieWidth, ComPhyAddr);
>
> DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
>
> - ComPhyPciePhyConfiguration (ComPhyAddr, HpipeAddr);
> + ComPhyPciePhyConfiguration (Lane, PcieWidth, PcieClk, ComPhyAddr, HpipeAddr);
>
> DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
>
> ComPhyPcieSetAnalogParameters (HpipeAddr);
>
> - DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));
> + DEBUG ((DEBUG_INFO, "%a: stage: ComPhy power up and check PLL\n", __FUNCTION__));
>
> - ComPhyPciePhyPowerUp (HpipeAddr);
> -
> - DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));
> -
> - Status = ComPhyPcieCheckPll (HpipeAddr);
> + Status = ComPhyPciePhyPowerUp (Lane, PcieWidth, ComPhyBase, HpipeBase);
>
> return Status;
> }
> @@ -1780,28 +1885,35 @@ ComPhyCp110Init (
> COMPHY_MAP *PtrComPhyMap, *SerdesMap;
> EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr;
> UINT32 ComPhyMaxCount, Lane;
> - UINT32 PcieBy4 = 1; // Indicating if first 4 lanes set to PCIE
> + UINT32 PcieWidth = 0;
> + UINT8 ChipId;
>
> ComPhyMaxCount = PtrChipCfg->LanesCount;
> ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr;
> HpipeBaseAddr = PtrChipCfg->Hpipe3BaseAddr;
> SerdesMap = PtrChipCfg->MapData;
> + ChipId = PtrChipCfg->ChipId;
>
> /* Config Comphy mux configuration */
> ComPhyMuxCp110(PtrChipCfg, SerdesMap);
>
> /* Check if the first 4 Lanes configured as By-4 */
> for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++, PtrComPhyMap++) {
> - if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0) {
> - PcieBy4 = 0;
> + if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0)
> break;
> - }
> + PcieWidth++;
> }
>
> for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < ComPhyMaxCount;
> Lane++, PtrComPhyMap++) {
> DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane));
> DEBUG((DEBUG_INFO, "ComPhy: Serdes Type = 0x%x\n", PtrComPhyMap->Type));
> +
> + if (Lane >= 4) {
> + /* PCIe lanes above the first 4 lanes, can be only by1 */
> + PcieWidth = 1;
> + }
> +
> switch (PtrComPhyMap->Type) {
> case COMPHY_TYPE_UNCONNECTED:
> continue;
> @@ -1810,7 +1922,7 @@ ComPhyCp110Init (
> case COMPHY_TYPE_PCIE1:
> case COMPHY_TYPE_PCIE2:
> case COMPHY_TYPE_PCIE3:
> - Status = ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr, ComPhyBaseAddr);
> + Status = ComPhyPciePowerUp (ChipId, Lane, PcieWidth, HpipeBaseAddr, ComPhyBaseAddr);
> break;
> case COMPHY_TYPE_SATA0:
> case COMPHY_TYPE_SATA1:
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> index bf21dca..b03bc35 100644
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> @@ -192,6 +192,7 @@ InitComPhyConfig (
> ChipConfig->Hpipe3BaseAddr = Desc->ComPhyHpipe3BaseAddresses[Id];
> ChipConfig->LanesCount = Desc->ComPhyLaneCount[Id];
> ChipConfig->MuxBitCount = Desc->ComPhyMuxBitCount[Id];
> + ChipConfig->ChipId = Id;
>
> /*
> * Below macro contains variable name concatenation (used to form PCD's name).
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> index 5899a4a..710ec80 100644
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> @@ -479,16 +479,29 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
>
> #define HPIPE_RST_CLK_CTRL_REG 0x704
> +#define HPIPE_RST_CLK_CTRL_CLR_ALL_MASK 0xffffffff
MAX_UINT32 ?
/
Leif
> #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
> #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
> #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
> #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_16 (0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
> #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
> #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET 4
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_MASK (0x3 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_1 (0x0 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_2 (0x1 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_4 (0x2 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_8 (0x3 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
> #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
>
> #define HPIPE_CLK_SRC_LO_REG 0x70c
> +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
> +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
> +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
> +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
> #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
> #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
>
> @@ -528,6 +541,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> #define COMMON_SELECTOR_PIPE_OFFSET 0x144
>
> #define COMMON_PHY_SD_CTRL1 0x148
> +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
> +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
> +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
> +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
> +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
> +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
> #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
> #define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
> #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
> @@ -594,6 +613,7 @@ struct _CHIP_COMPHY_CONFIG {
> COMPHY_CHIP_INIT Init;
> UINT32 LanesCount;
> UINT32 MuxBitCount;
> + UINT8 ChipId;
> };
>
> VOID
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> index a1584b4..f00180c 100644
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> @@ -49,6 +49,7 @@
> ArmLib
> DebugLib
> MemoryAllocationLib
> + MvSARLib
> PcdLib
> IoLib
>
> --
> 2.7.4
>
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