Some more patches for SynQuacer, for PCIe and SMMU support.

Patch #1 was contributed by Kojima-san, and enables another quirk in the
Synopsys IP to work around issues with Samsung 970 SSDs

Patch #2 adds a couple of level 3 tables to the static page table region
in the NOR flash so that ARM-TF can easily reprogram the north SMMU to
present the ECAM spaces in a sane manner. This patch only implements the
static page table entries, the code to program it needs to run in the secure
world, and will be added to ARM-TF.

Patch #3 enables the SMMU for the netsec and SDHCI controllers.

Ard Biesheuvel (2):
  Silicon/Socionext/SynQuacer/Stage2Tables: add north SMMU level 3 table
  Silicon/SynQuacer/AcpiTables: add NETSEC/eMMC SMMU to the IORT

Masahisa KOJIMA (1):
  Silicon/SynQuacerPciHostBridgeLib: add workaround for PCIe MMIO64

 .../Socionext/SynQuacer/AcpiTables/Iort.aslc  | 109 +++++++++++++++++-
 .../SynQuacerPciHostBridgeLibConstructor.c    |   5 +-
 .../SynQuacer/Stage2Tables/Stage2Tables.S     |  35 ++++--
 3 files changed, 136 insertions(+), 13 deletions(-)

-- 
2.17.0

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