Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
---
v2:
 - s/outer execution loop/main loop
 - Mention re-evaluation of cpu_exec_interrupt()
 - Changed wording on lookup_and_goto_ptr()
 - Added more details to step 2 of goto+tb + exit_tb
 - Added details about when goto_tb + exit_tb cannot be used

 docs/devel/tcg.rst | 105 +++++++++++++++++++++++++++++++++++++++------
 1 file changed, 93 insertions(+), 12 deletions(-)

diff --git a/docs/devel/tcg.rst b/docs/devel/tcg.rst
index 4ebde44b9d..9cc56df22a 100644
--- a/docs/devel/tcg.rst
+++ b/docs/devel/tcg.rst
@@ -11,13 +11,14 @@ performances.
 QEMU's dynamic translation backend is called TCG, for "Tiny Code
 Generator". For more information, please take a look at ``tcg/README``.
 
-Some notable features of QEMU's dynamic translator are:
+The following sections outline some notable features and implementation
+details of QEMU's dynamic translator.
 
 CPU state optimisations
 -----------------------
 
-The target CPUs have many internal states which change the way it
-evaluates instructions. In order to achieve a good speed, the
+The target CPUs have many internal states which change the way they
+evaluate instructions. In order to achieve a good speed, the
 translation phase considers that some state information of the virtual
 CPU cannot change in it. The state is recorded in the Translation
 Block (TB). If the state changes (e.g. privilege level), a new TB will
@@ -31,17 +32,97 @@ Direct block chaining
 ---------------------
 
 After each translated basic block is executed, QEMU uses the simulated
-Program Counter (PC) and other cpu state information (such as the CS
+Program Counter (PC) and other CPU state information (such as the CS
 segment base value) to find the next basic block.
 
-In order to accelerate the most common cases where the new simulated PC
-is known, QEMU can patch a basic block so that it jumps directly to the
-next one.
-
-The most portable code uses an indirect jump. An indirect jump makes
-it easier to make the jump target modification atomic. On some host
-architectures (such as x86 or PowerPC), the ``JUMP`` opcode is
-directly patched so that the block chaining has no overhead.
+In its simplest, less optimized form, this is done by exiting from the
+current TB, going through the TB epilogue, and then back to the
+main loop. That’s where QEMU looks for the next TB to execute,
+translating it from the guest architecture if it isn’t already available
+in memory. Then QEMU proceeds to execute this next TB, starting at the
+prologue and then moving on to the translated instructions.
+
+Exiting from the TB this way will cause the ``cpu_exec_interrupt()``
+callback to be re-evaluated before executing additional instructions.
+It is mandatory to exit this way after any CPU state changes that may
+unmask interrupts.
+
+In order to accelerate the most common cases where the TB for the new
+simulated PC is already available, QEMU has mechanisms that allow
+multiple TBs to be chained directly, without having to go back to the
+main loop as described above. These mechanisms are:
+
+``lookup_and_goto_ptr``
+^^^^^^^^^^^^^^^^^^^^^^^
+
+Calling ``tcg_gen_lookup_and_goto_ptr()`` will emit a call to
+``helper_lookup_tb_ptr``. This helper will look for an existing TB that
+matches the current CPU state. If the destination TB is available its
+code address is returned, otherwise the address of the JIT epilogue is
+returned. The call to the helper is always followed by the tcg ``goto_ptr``
+opcode, which branches to the returned address. In this way, we either
+branch to the next TB or return to the main loop.
+
+``goto_tb + exit_tb``
+^^^^^^^^^^^^^^^^^^^^^
+
+The translation code usually implements branching by performing the
+following steps:
+
+1. Call ``tcg_gen_goto_tb()`` passing a jump slot index (either 0 or 1)
+   as a parameter.
+
+2. Emit TCG instructions to update the CPU state with any information
+   that has been assumed constant and is required by the main loop to
+   correctly locate and execute the next TB. For most guests, this is
+   just the PC of the branch destination, but others may store additional
+   data. The information updated in this step must be inferable from both
+   ``cpu_get_tb_cpu_state()`` and ``cpu_restore_state()``.
+
+3. Call ``tcg_gen_exit_tb()`` passing the address of the current TB and
+   the jump slot index again.
+
+Step 1, ``tcg_gen_goto_tb()``, will emit a ``goto_tb`` TCG
+instruction that later on gets translated to a jump to an address
+associated with the specified jump slot. Initially, this is the address
+of step 2's instructions, which update the CPU state information. Step 3,
+``tcg_gen_exit_tb()``, exits from the current TB returning a tagged
+pointer composed of the last executed TB’s address and the jump slot
+index.
+
+The first time this whole sequence is executed, step 1 simply jumps
+to step 2. Then the CPU state information gets updated and we exit from
+the current TB. As a result, the behavior is very similar to the less
+optimized form described earlier in this section.
+
+Next, the main loop looks for the next TB to execute using the
+current CPU state information (creating the TB if it wasn’t already
+available) and, before starting to execute the new TB’s instructions,
+patches the previously executed TB by associating one of its jump
+slots (the one specified in the call to ``tcg_gen_exit_tb()``) with the
+address of the new TB.
+
+The next time this previous TB is executed and we get to that same
+``goto_tb`` step, it will already be patched (assuming the destination TB
+is still in memory) and will jump directly to the first instruction of
+the destination TB, without going back to the main loop.
+
+For the ``goto_tb + exit_tb`` mechanism to be used, the following
+conditions need to be satisfied:
+
+* The change in CPU state must be constant, e.g., a direct branch and
+  not an indirect branch.
+
+* The direct branch cannot cross a page boundary. Memory mappings
+  may change, causing the code at the destination address to change.
+
+Note that, on step 3 (``tcg_gen_exit_tb()``), in addition to the
+jump slot index, the address of the TB just executed is also returned.
+This is important because that's the TB that will have to be patched
+by the main loop, and not necessarily the one that was directly
+executed from it. This is due to the fact that the original TB might
+have already been chained to additional TBs, which ended up being
+executed without the main loop's knowledge.
 
 Self-modifying code and translated code invalidation
 ----------------------------------------------------
-- 
2.25.1

I don't know enough about the technical information to say if the docs 
are correct, but there were 2 paragraphs where I think wording could be 
improved to make the explanation more clear.

On 31/05/2021 18:14, Luis Pires wrote:
> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
> ---
> v2:
>   - s/outer execution loop/main loop
>   - Mention re-evaluation of cpu_exec_interrupt()
>   - Changed wording on lookup_and_goto_ptr()
>   - Added more details to step 2 of goto+tb + exit_tb
>   - Added details about when goto_tb + exit_tb cannot be used
>
>   docs/devel/tcg.rst | 105 +++++++++++++++++++++++++++++++++++++++------
>   1 file changed, 93 insertions(+), 12 deletions(-)
>
> diff --git a/docs/devel/tcg.rst b/docs/devel/tcg.rst
> index 4ebde44b9d..9cc56df22a 100644
> --- a/docs/devel/tcg.rst
> +++ b/docs/devel/tcg.rst
> @@ -11,13 +11,14 @@ performances.
>   QEMU's dynamic translation backend is called TCG, for "Tiny Code
>   Generator". For more information, please take a look at ``tcg/README``.
>   
> -Some notable features of QEMU's dynamic translator are:
> +The following sections outline some notable features and implementation
> +details of QEMU's dynamic translator.
>   
>   CPU state optimisations
>   -----------------------
>   
> -The target CPUs have many internal states which change the way it
> -evaluates instructions. In order to achieve a good speed, the
> +The target CPUs have many internal states which change the way they
> +evaluate instructions. In order to achieve a good speed, the
>   translation phase considers that some state information of the virtual
>   CPU cannot change in it. The state is recorded in the Translation
>   Block (TB). If the state changes (e.g. privilege level), a new TB will
> @@ -31,17 +32,97 @@ Direct block chaining
>   ---------------------
>   
>   After each translated basic block is executed, QEMU uses the simulated
> -Program Counter (PC) and other cpu state information (such as the CS
> +Program Counter (PC) and other CPU state information (such as the CS
>   segment base value) to find the next basic block.
>   
> -In order to accelerate the most common cases where the new simulated PC
> -is known, QEMU can patch a basic block so that it jumps directly to the
> -next one.
> -
> -The most portable code uses an indirect jump. An indirect jump makes
> -it easier to make the jump target modification atomic. On some host
> -architectures (such as x86 or PowerPC), the ``JUMP`` opcode is
> -directly patched so that the block chaining has no overhead.
> +In its simplest, less optimized form, this is done by exiting from the
> +current TB, going through the TB epilogue, and then back to the
> +main loop. That’s where QEMU looks for the next TB to execute,
> +translating it from the guest architecture if it isn’t already available
> +in memory. Then QEMU proceeds to execute this next TB, starting at the
> +prologue and then moving on to the translated instructions.
> +
> +Exiting from the TB this way will cause the ``cpu_exec_interrupt()``
> +callback to be re-evaluated before executing additional instructions.
> +It is mandatory to exit this way after any CPU state changes that may
> +unmask interrupts.
> +
> +In order to accelerate the most common cases where the TB for the new
> +simulated PC is already available, QEMU has mechanisms that allow
> +multiple TBs to be chained directly, without having to go back to the
> +main loop as described above. These mechanisms are:

I feel like there is either a comma missing or the paragraph can be 
reordered a bit here. The way it is written means that there are many 
cases where the TB is already available and you'll be explaining how the 
handle the most common of such cases, but by changing the first line to

-In order to accelerate the most common cases where the TB for the new

+In order to accelerate the most common cases, where the TB for the new

You get many cases, the most common of which is the TB being already in 
memory. This sounds to me like the more reasonable, but incorrect, read 
of the paragraph. If I am mistaken and there are indeed many cases where 
the TB is already in memory, I think maybe it can be reordered to make 
this read less likely to happen, by saying something like:

QEMU has mechanisms that allow multiple TBs to be chained directly 
(without having to go back to the main loop described above) that can 
accelerate the most common cases of the TB for the new simulated PC 
already being available.

> +
> +``lookup_and_goto_ptr``
> +^^^^^^^^^^^^^^^^^^^^^^^
> +
> +Calling ``tcg_gen_lookup_and_goto_ptr()`` will emit a call to
> +``helper_lookup_tb_ptr``. This helper will look for an existing TB that
> +matches the current CPU state. If the destination TB is available its
> +code address is returned, otherwise the address of the JIT epilogue is
> +returned. The call to the helper is always followed by the tcg ``goto_ptr``
> +opcode, which branches to the returned address. In this way, we either
> +branch to the next TB or return to the main loop.
> +
> +``goto_tb + exit_tb``
> +^^^^^^^^^^^^^^^^^^^^^
> +
> +The translation code usually implements branching by performing the
> +following steps:
> +
> +1. Call ``tcg_gen_goto_tb()`` passing a jump slot index (either 0 or 1)
> +   as a parameter.
> +
> +2. Emit TCG instructions to update the CPU state with any information
> +   that has been assumed constant and is required by the main loop to
> +   correctly locate and execute the next TB. For most guests, this is
> +   just the PC of the branch destination, but others may store additional
> +   data. The information updated in this step must be inferable from both
> +   ``cpu_get_tb_cpu_state()`` and ``cpu_restore_state()``.
> +
> +3. Call ``tcg_gen_exit_tb()`` passing the address of the current TB and
> +   the jump slot index again.
> +
> +Step 1, ``tcg_gen_goto_tb()``, will emit a ``goto_tb`` TCG
> +instruction that later on gets translated to a jump to an address
> +associated with the specified jump slot. Initially, this is the address
> +of step 2's instructions, which update the CPU state information. Step 3,
> +``tcg_gen_exit_tb()``, exits from the current TB returning a tagged
> +pointer composed of the last executed TB’s address and the jump slot
> +index.
> +
> +The first time this whole sequence is executed, step 1 simply jumps
> +to step 2. Then the CPU state information gets updated and we exit from
> +the current TB. As a result, the behavior is very similar to the less
> +optimized form described earlier in this section.
> +
> +Next, the main loop looks for the next TB to execute using the
> +current CPU state information (creating the TB if it wasn’t already
> +available) and, before starting to execute the new TB’s instructions,
> +patches the previously executed TB by associating one of its jump
> +slots (the one specified in the call to ``tcg_gen_exit_tb()``) with the
> +address of the new TB.
> +
> +The next time this previous TB is executed and we get to that same
> +``goto_tb`` step, it will already be patched (assuming the destination TB
> +is still in memory) and will jump directly to the first instruction of
> +the destination TB, without going back to the main loop.
> +
> +For the ``goto_tb + exit_tb`` mechanism to be used, the following
> +conditions need to be satisfied:
> +
> +* The change in CPU state must be constant, e.g., a direct branch and
> +  not an indirect branch.
> +
> +* The direct branch cannot cross a page boundary. Memory mappings
> +  may change, causing the code at the destination address to change.
> +
> +Note that, on step 3 (``tcg_gen_exit_tb()``), in addition to the
> +jump slot index, the address of the TB just executed is also returned.
> +This is important because that's the TB that will have to be patched
> +by the main loop, and not necessarily the one that was directly
> +executed from it. This is due to the fact that the original TB might
> +have already been chained to additional TBs, which ended up being
> +executed without the main loop's knowledge.

This last paragraph is a bit tough to read, but I don't know a better 
way to write it, so it may just be that this 3rd step is a bit confusing 
at first. Maybe something like:

-This is important because that's the TB that will have to be patched
-by the main loop, and not necessarily the one that was directly
-executed from it. This is due to the fact that the original TB might
-have already been chained to additional TBs, which ended up being
-executed without the main loop's knowledge.
+This address corresponds to the TB that will be patched; it may be
+different than the one that was just executed if the latter has already
+been chained to other TBs.

Could be a bit more clear?

>   
>   Self-modifying code and translated code invalidation
>   ----------------------------------------------------
-- 
Bruno Piazera Larsen
Instituto de Pesquisas ELDORADO 
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

From: Bruno Piazera Larsen <bruno.larsen@eldorado.org.br> 
> I feel like there is either a comma missing or the paragraph can be reordered a bit here. The way it is written means that there are many cases where the TB is already available and you'll be explaining how the handle the most common of such cases, but by changing the first line to
> -In order to accelerate the most common cases where the TB for the new
> +In order to accelerate the most common cases, where the TB for the new
> You get many cases, the most common of which is the TB being already in memory. This sounds to me like the more reasonable, but incorrect, read of the paragraph. If I am mistaken and there are indeed many cases where the TB is already in memory, I think maybe it can be reordered to make this read less likely to happen, by saying something like:
> QEMU has mechanisms that allow multiple TBs to be chained directly (without having to go back to the main loop described above) that can accelerate the most common cases of the TB for the new simulated PC already being available.

I'll just drop the bit about being the most common case, as it's irrelevant.

> This last paragraph is a bit tough to read, but I don't know a better way to write it, so it may just be that this 3rd step is a bit confusing at first. Maybe something like:
> -This is important because that's the TB that will have to be patched
> -by the main loop, and not necessarily the one that was directly
> -executed from it. This is due to the fact that the original TB might
> -have already been chained to additional TBs, which ended up being
> -executed without the main loop's knowledge.
> +This address corresponds to the TB that will be patched; it may be
> +different than the one that was just executed if the latter has already
> +been chained to other TBs.

That wouldn't be accurate. The returned address IS the address of the TB that was just executed. But the way you wrote is more direct. I'll send a new version of the patch that incorporates it with a few adjustments.

--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>