[PATCH 0/2] target/riscv: fix hypervisor exceptions

Jose Martins posted 2 patches 2 years, 10 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/next-importer-push tags/patchew/20210602191125.525742-1-josemartins90@gmail.com
Maintainers: Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Bin Meng <bin.meng@windriver.com>
target/riscv/cpu.h        |  2 --
target/riscv/cpu_bits.h   |  6 -----
target/riscv/cpu_helper.c | 54 +++++++--------------------------------
3 files changed, 9 insertions(+), 53 deletions(-)
[PATCH 0/2] target/riscv: fix hypervisor exceptions
Posted by Jose Martins 2 years, 10 months ago
This patch series fixes the forwarding of VS-level execptions to HS-mode and
removes unecessary code previously used for the routing of exceptions to    
HS-mode.

Jose Martins (2):
  target/riscv: fix VS interrupts forwarding to HS
  target/riscv: remove force HS exception

 target/riscv/cpu.h        |  2 --
 target/riscv/cpu_bits.h   |  6 -----
 target/riscv/cpu_helper.c | 54 +++++++--------------------------------
 3 files changed, 9 insertions(+), 53 deletions(-)

-- 
2.30.2