On Fri, 20 May 2022 17:37:30 +0100
Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
> The initial CXL support including support on x86/pc has now merged
> (thanks Michael!).
>
> This is the first of the two remaining parts of that series, unchanged
> since v10. The second is CXL switch support which can be applied
> separately to this series and will be sent shortly.
>
> CXL support requires two types of memory regions and this hooks them
> up in arm/virt.
>
> 1) CXL host bridge control register regions. This allows for up to
> 16 host bridges which should keep anyone happy. The CEDT ACPI table
> is used by system software to find these regions.
> 2) CXL Fixed Memory Windows. CFMWs are regions of PA space that are
> configured to perform interleaved accesses over multiple host bridges.
> They are fixed, but the OS may select between multiple CFMWs to find
> one suitable for the interleave it desires. All interleave in the
> host bridges and switches is programmable and discoverable - only
> these top level regions are static and described to system software
> via another structure in CEDT.
>
> A simple test cases is added to existing cxl-test qtest.
>
> Jonathan Cameron (2):
> hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances
> pxb-cxl
> qtest/cxl: Add aarch64 virt test for CXL
>
> hw/arm/virt-acpi-build.c | 33 +++++++++++++++++++++++++++
> hw/arm/virt.c | 40 ++++++++++++++++++++++++++++++++-
> include/hw/arm/virt.h | 1 +
> tests/qtest/cxl-test.c | 48 ++++++++++++++++++++++++++++++++--------
> tests/qtest/meson.build | 1 +
> 5 files changed, 113 insertions(+), 10 deletions(-)
>
Note I'll send out a v12 of this series after resolving Paolo's
feedback on the main CXL series that proceeded this.
Principal impacts on this series will be updated tests for the
new command line and a move of CXLState into the virt machine
specific state structure.
Thanks,
Jonathan