[v2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next

[PATCH v2 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next

Posted by Daniel Henrique Barboza 1 year, 3 months ago

Hi,

In this version I fixed the commit message typos pointed by Bin. I've
also added some notes about the code repetition the fix is introducing
in the cpu_init() functions.

The patches are based on riscv-to-apply.next at c1e76da3e668
("target/riscv/cpu.c: Fix elen check").

Changes from v1:
- patch 1:
  - fixed commit message typos
v1 review: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02035.html

Daniel Henrique Barboza (2):
  target/riscv/cpu: set cpu->cfg in register_cpu_props()
  target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()

 target/riscv/cpu.c | 439 +++++++++++++++++++++++++--------------------
 target/riscv/cpu.h |   4 +
 2 files changed, 249 insertions(+), 194 deletions(-)

-- 
2.39.0

Re: [PATCH v2 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next

Posted by Alistair Francis 1 year, 3 months ago

On Sat, Jan 14, 2023 at 3:55 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> In this version I fixed the commit message typos pointed by Bin. I've
> also added some notes about the code repetition the fix is introducing
> in the cpu_init() functions.
>
> The patches are based on riscv-to-apply.next at c1e76da3e668
> ("target/riscv/cpu.c: Fix elen check").
>
> Changes from v1:
> - patch 1:
>   - fixed commit message typos
> v1 review: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02035.html
>
> Daniel Henrique Barboza (2):
>   target/riscv/cpu: set cpu->cfg in register_cpu_props()
>   target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c | 439 +++++++++++++++++++++++++--------------------
>  target/riscv/cpu.h |   4 +
>  2 files changed, 249 insertions(+), 194 deletions(-)
>
> --
> 2.39.0
>
>