[PATCH] include/hw/riscv/opentitan: update opentitan IRQs

Wilfred Mallawa posted 1 patch 2 weeks, 3 days ago
There is a newer version of this series
include/hw/riscv/opentitan.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
[PATCH] include/hw/riscv/opentitan: update opentitan IRQs
Posted by Wilfred Mallawa 2 weeks, 3 days ago
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Updates the opentitan IRQs to match the latest supported commit of
Opentitan from TockOS.

OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
 include/hw/riscv/opentitan.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 7659d1bc5b..235728b9cc 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -108,11 +108,11 @@ enum {
     IBEX_UART0_RX_BREAK_ERR_IRQ   = 6,
     IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
     IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
-    IBEX_TIMER_TIMEREXPIRED0_0    = 127,
-    IBEX_SPI_HOST0_ERR_IRQ        = 134,
-    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 135,
-    IBEX_SPI_HOST1_ERR_IRQ        = 136,
-    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 137,
+    IBEX_TIMER_TIMEREXPIRED0_0    = 124,
+    IBEX_SPI_HOST0_ERR_IRQ        = 131,
+    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 132,
+    IBEX_SPI_HOST1_ERR_IRQ        = 133,
+    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 134,
 };
 
 #endif
-- 
2.39.0
Re: [PATCH] include/hw/riscv/opentitan: update opentitan IRQs
Posted by Alistair Francis 2 weeks, 3 days ago
On Mon, Jan 23, 2023 at 10:06 AM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> Updates the opentitan IRQs to match the latest supported commit of
> Opentitan from TockOS.
>
> OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  include/hw/riscv/opentitan.h | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 7659d1bc5b..235728b9cc 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -108,11 +108,11 @@ enum {
>      IBEX_UART0_RX_BREAK_ERR_IRQ   = 6,
>      IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
>      IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
> -    IBEX_TIMER_TIMEREXPIRED0_0    = 127,
> -    IBEX_SPI_HOST0_ERR_IRQ        = 134,
> -    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 135,
> -    IBEX_SPI_HOST1_ERR_IRQ        = 136,
> -    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 137,
> +    IBEX_TIMER_TIMEREXPIRED0_0    = 124,
> +    IBEX_SPI_HOST0_ERR_IRQ        = 131,
> +    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 132,
> +    IBEX_SPI_HOST1_ERR_IRQ        = 133,
> +    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 134,
>  };
>
>  #endif
> --
> 2.39.0
>
>