Just realized that the subject doesn't mention 'riscv' anywhere.
Yes, this is target/riscv specific. I'll make sure to mention that in the
future versions.
Thanks,
Daniel
On 3/8/23 17:19, Daniel Henrique Barboza wrote:
> Hi,
>
> During the review of a series that did some work in the RISCV_FEATURES*
> enum, Liu Zhiwei commented on how we could centralize the all the
> extension validation code and integrate it with write_misa() [1].
>
> This does at least part of what was suggested. The idea is that, ATM, we
> have too many places setting cpu->cfg and the validation logic is
> scattered around (e.g. there are some contraints in write_misa() that
> should be applicable elsewhere). This series is an attempt to centralize
> things a bit.
>
> The main accomplishments of this series are:
>
> - the parent device riscv-cpu no longer sets any cpu->cfg attribute. This
> was forcing init() functions to disable extensions that it wouldn't
> use just because the parent device was enabling it;
>
> - all validations are centered in validate_set_extensions(), with
> pontual exceptions in write_misa() that has exclusive contraints;
>
> - set_misa() now writes cpu->cfg. No need to have one function to set
> env->misa_ext and then another to set cpu->cfg;
>
> - register_cpu_props() now only exposes user-facing props;
>
> - all validations from validate_set_extensions() are done at the start
> of the function. Validate first, set extensions after;
>
> - RVE is now forbidden in all validations, not just in write_misa();
>
> - RVG is now forbidden in write_misa();
>
> - write_misa now uses set_misa() and validate_set_extensions().
>
>
>
> [1] https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg05092.html
>
> Daniel Henrique Barboza (17):
> target/riscv/cpu.c: add riscv_cpu_validate_v()
> target/riscv/cpu.c: remove set_vext_version()
> target/riscv/cpu.c: remove set_priv_version()
> target/riscv: add PRIV_VERSION_LATEST macro
> target/riscv/cpu.c: add riscv_cpu_validate_priv_spec()
> target/riscv: move realize() validations to
> riscv_cpu_validate_set_extensions()
> target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
> target/riscv/cpu.c: avoid set_misa() in validate_set_extensions()
> target/riscv/cpu.c: set cpu config in set_misa()
> target/riscv/cpu.c: redesign register_cpu_props()
> target/riscv/cpu.c: move riscv_cpu_validate_v() up
> target/riscv: put env->misa_ext <-> cpu->cfg code into helpers
> target/riscv/cpu.c: split riscv_cpu_validate_priv_spec()
> target/riscv/cpu.c: do not allow RVE to be set
> target/riscv: add RVG
> target/riscv: do not allow RVG in write_misa()
> target/riscv: rework write_misa()
>
> target/riscv/cpu.c | 516 +++++++++++++++++++++++++--------------------
> target/riscv/cpu.h | 9 +-
> target/riscv/csr.c | 52 ++---
> 3 files changed, 323 insertions(+), 254 deletions(-)
>