On PCI init PCI bridges may need some
extra info about bus number to reserve, IO, memory and
prefetchable memory limits. QEMU can provide this
with a special vendor-specific PCI capability.
Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com>
---
hw/pci/pci_bridge.c | 37 +++++++++++++++++++++++++++++++++++++
include/hw/pci/pci_bridge.h | 28 ++++++++++++++++++++++++++++
2 files changed, 65 insertions(+)
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 720119b..e9f12d6 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -408,6 +408,43 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
br->bus_name = bus_name;
}
+
+int pci_bridge_qemu_cap_init(PCIDevice *dev, int cap_offset,
+ uint8_t bus_reserve, uint32_t io_reserve,
+ uint16_t non_pref_reserve, uint64_t pref_reserve,
+ Error **errp)
+{
+ size_t cap_len = sizeof(PCIBridgeQemuCap);
+ PCIBridgeQemuCap cap = {
+ .len = cap_len,
+ .type = REDHAT_PCI_CAP_QEMU,
+ .bus_res = bus_reserve,
+ .non_pref_16 = non_pref_reserve
+ };
+
+ if ((uint8_t)io_reserve == io_reserve) {
+ cap.io_8 = io_reserve;
+ } else {
+ cap.io_32 = io_reserve;
+ }
+ if ((uint16_t)pref_reserve == pref_reserve) {
+ cap.pref_32 = pref_reserve;
+ } else {
+ cap.pref_64 = pref_reserve;
+ }
+
+ int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
+ cap_offset, cap_len, errp);
+ if (offset < 0) {
+ return offset;
+ }
+
+ memcpy(dev->config + offset + PCI_CAP_FLAGS,
+ (char *)&cap + PCI_CAP_FLAGS,
+ cap_len - PCI_CAP_FLAGS);
+ return 0;
+}
+
static const TypeInfo pci_bridge_type_info = {
.name = TYPE_PCI_BRIDGE,
.parent = TYPE_PCI_DEVICE,
diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h
index ff7cbaa..e9b7cf4 100644
--- a/include/hw/pci/pci_bridge.h
+++ b/include/hw/pci/pci_bridge.h
@@ -67,4 +67,32 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
#define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
#define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
+typedef struct PCIBridgeQemuCap {
+ uint8_t id; /* Standard PCI capability header field */
+ uint8_t next; /* Standard PCI capability header field */
+ uint8_t len; /* Standard PCI vendor-specific capability header field */
+ uint8_t type; /* Red Hat vendor-specific capability type.
+ Types are defined with REDHAT_PCI_CAP_ prefix */
+
+ uint16_t non_pref_16; /* Non-prefetchable memory limit */
+ uint8_t bus_res; /* Minimum number of buses to reserve */
+ uint8_t io_8; /* IO space limit in case of 8-bit value */
+ uint32_t io_32; /* IO space limit in case of 32-bit value
+ This 2 values are mutually exclusive,
+ i.e. they can't be >0 both*/
+ uint32_t pref_32; /* Prefetchable memory limit
+ in case of 32-bit value */
+ uint64_t pref_64; /* Prefetchable memory limit
+ in case of 64-bit value
+ This 2 values are mutually exclusive (just as
+ IO limit), i.e. they can't be >0 both */
+} PCIBridgeQemuCap;
+
+#define REDHAT_PCI_CAP_QEMU 1
+
+int pci_bridge_qemu_cap_init(PCIDevice *dev, int cap_offset,
+ uint8_t bus_reserve, uint32_t io_reserve,
+ uint16_t mem_reserve, uint64_t pref_reserve,
+ Error **errp);
+
#endif /* QEMU_PCI_BRIDGE_H */
--
2.7.4
_______________________________________________
SeaBIOS mailing list
SeaBIOS@seabios.org
https://mail.coreboot.org/mailman/listinfo/seabios
On 29/07/2017 2:37, Aleksandr Bezzubikov wrote:
> On PCI init PCI bridges may need some
> extra info about bus number to reserve, IO, memory and
> prefetchable memory limits. QEMU can provide this
> with a special vendor-specific PCI capability.
>
> Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com>
> ---
> hw/pci/pci_bridge.c | 37 +++++++++++++++++++++++++++++++++++++
> include/hw/pci/pci_bridge.h | 28 ++++++++++++++++++++++++++++
> 2 files changed, 65 insertions(+)
>
> diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
> index 720119b..e9f12d6 100644
> --- a/hw/pci/pci_bridge.c
> +++ b/hw/pci/pci_bridge.c
> @@ -408,6 +408,43 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
> br->bus_name = bus_name;
> }
>
Hi Alexksander,
> +
> +int pci_bridge_qemu_cap_init(PCIDevice *dev, int cap_offset,
> + uint8_t bus_reserve, uint32_t io_reserve,
> + uint16_t non_pref_reserve, uint64_t pref_reserve,
> + Error **errp)
Maybe we should change it to something like
pci_bridge_res_reseve_cap_init ? Maybe we will
have other caps in the future.
> +{
> + size_t cap_len = sizeof(PCIBridgeQemuCap);
> + PCIBridgeQemuCap cap = {
> + .len = cap_len,
> + .type = REDHAT_PCI_CAP_QEMU,
> + .bus_res = bus_reserve,
> + .non_pref_16 = non_pref_reserve
> + };
> +
> + if ((uint8_t)io_reserve == io_reserve) {
> + cap.io_8 = io_reserve;
> + } else {
> + cap.io_32 = io_reserve;
> + }
> + if ((uint16_t)pref_reserve == pref_reserve) {
> + cap.pref_32 = pref_reserve;
> + } else {
> + cap.pref_64 = pref_reserve;
> + }
> +
> + int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
> + cap_offset, cap_len, errp);
> + if (offset < 0) {
> + return offset;
> + }
> +
> + memcpy(dev->config + offset + PCI_CAP_FLAGS,
> + (char *)&cap + PCI_CAP_FLAGS,
> + cap_len - PCI_CAP_FLAGS);
> + return 0;
> +}
> +
> static const TypeInfo pci_bridge_type_info = {
> .name = TYPE_PCI_BRIDGE,
> .parent = TYPE_PCI_DEVICE,
> diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h
> index ff7cbaa..e9b7cf4 100644
> --- a/include/hw/pci/pci_bridge.h
> +++ b/include/hw/pci/pci_bridge.h
> @@ -67,4 +67,32 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
> #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
> #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
>
> +typedef struct PCIBridgeQemuCap {
> + uint8_t id; /* Standard PCI capability header field */
> + uint8_t next; /* Standard PCI capability header field */
> + uint8_t len; /* Standard PCI vendor-specific capability header field */
> + uint8_t type; /* Red Hat vendor-specific capability type.
> + Types are defined with REDHAT_PCI_CAP_ prefix */
> +
> + uint16_t non_pref_16; /* Non-prefetchable memory limit */
> + uint8_t bus_res; /* Minimum number of buses to reserve */
> + uint8_t io_8; /* IO space limit in case of 8-bit value */
> + uint32_t io_32; /* IO space limit in case of 32-bit value
> + This 2 values are mutually exclusive,
> + i.e. they can't be >0 both*/
> + uint32_t pref_32; /* Prefetchable memory limit
> + in case of 32-bit value */
> + uint64_t pref_64; /* Prefetchable memory limit
> + in case of 64-bit value
> + This 2 values are mutually exclusive (just as
> + IO limit), i.e. they can't be >0 both */
The same comments as for the SeaBIOS series, can the capability
be more simple?
uint32_t bus_res
uint32_t io_res
uint32_t mem_res
uint32_t pref_32_res
uint64_t pref_64_res
It is possible I missed some arguments, I'll have another look
on the thread.
Thanks,
Marcel
> +} PCIBridgeQemuCap;
> +
> +#define REDHAT_PCI_CAP_QEMU 1
> +
> +int pci_bridge_qemu_cap_init(PCIDevice *dev, int cap_offset,
> + uint8_t bus_reserve, uint32_t io_reserve,
> + uint16_t mem_reserve, uint64_t pref_reserve,
> + Error **errp);
> +
> #endif /* QEMU_PCI_BRIDGE_H */
>
2017-07-31 14:29 GMT+03:00 Marcel Apfelbaum <marcel@redhat.com>:
> On 29/07/2017 2:37, Aleksandr Bezzubikov wrote:
>>
>> On PCI init PCI bridges may need some
>> extra info about bus number to reserve, IO, memory and
>> prefetchable memory limits. QEMU can provide this
>> with a special vendor-specific PCI capability.
>>
>> Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com>
>> ---
>> hw/pci/pci_bridge.c | 37 +++++++++++++++++++++++++++++++++++++
>> include/hw/pci/pci_bridge.h | 28 ++++++++++++++++++++++++++++
>> 2 files changed, 65 insertions(+)
>>
>> diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
>> index 720119b..e9f12d6 100644
>> --- a/hw/pci/pci_bridge.c
>> +++ b/hw/pci/pci_bridge.c
>> @@ -408,6 +408,43 @@ void pci_bridge_map_irq(PCIBridge *br, const char*
>> bus_name,
>> br->bus_name = bus_name;
>> }
>>
>
> Hi Alexksander,
>
>
>> +
>> +int pci_bridge_qemu_cap_init(PCIDevice *dev, int cap_offset,
>> + uint8_t bus_reserve, uint32_t io_reserve,
>> + uint16_t non_pref_reserve, uint64_t
>> pref_reserve,
>> + Error **errp)
>
>
> Maybe we should change it to something like
> pci_bridge_res_reseve_cap_init ? Maybe we will
> have other caps in the future.
>
>
>> +{
>> + size_t cap_len = sizeof(PCIBridgeQemuCap);
>> + PCIBridgeQemuCap cap = {
>> + .len = cap_len,
>> + .type = REDHAT_PCI_CAP_QEMU,
>> + .bus_res = bus_reserve,
>> + .non_pref_16 = non_pref_reserve
>> + };
>> +
>> + if ((uint8_t)io_reserve == io_reserve) {
>> + cap.io_8 = io_reserve;
>> + } else {
>> + cap.io_32 = io_reserve;
>> + }
>> + if ((uint16_t)pref_reserve == pref_reserve) {
>> + cap.pref_32 = pref_reserve;
>> + } else {
>> + cap.pref_64 = pref_reserve;
>> + }
>> +
>> + int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
>> + cap_offset, cap_len, errp);
>> + if (offset < 0) {
>> + return offset;
>> + }
>> +
>> + memcpy(dev->config + offset + PCI_CAP_FLAGS,
>> + (char *)&cap + PCI_CAP_FLAGS,
>> + cap_len - PCI_CAP_FLAGS);
>> + return 0;
>> +}
>> +
>> static const TypeInfo pci_bridge_type_info = {
>> .name = TYPE_PCI_BRIDGE,
>> .parent = TYPE_PCI_DEVICE,
>> diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h
>> index ff7cbaa..e9b7cf4 100644
>> --- a/include/hw/pci/pci_bridge.h
>> +++ b/include/hw/pci/pci_bridge.h
>> @@ -67,4 +67,32 @@ void pci_bridge_map_irq(PCIBridge *br, const char*
>> bus_name,
>> #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer
>> status */
>> #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR#
>> enable */
>> +typedef struct PCIBridgeQemuCap {
>> + uint8_t id; /* Standard PCI capability header field */
>> + uint8_t next; /* Standard PCI capability header field */
>> + uint8_t len; /* Standard PCI vendor-specific capability header
>> field */
>> + uint8_t type; /* Red Hat vendor-specific capability type.
>> + Types are defined with REDHAT_PCI_CAP_ prefix */
>> +
>> + uint16_t non_pref_16; /* Non-prefetchable memory limit */
>> + uint8_t bus_res; /* Minimum number of buses to reserve */
>> + uint8_t io_8; /* IO space limit in case of 8-bit value */
>> + uint32_t io_32; /* IO space limit in case of 32-bit value
>> + This 2 values are mutually exclusive,
>> + i.e. they can't be >0 both*/
>> + uint32_t pref_32; /* Prefetchable memory limit
>> + in case of 32-bit value */
>> + uint64_t pref_64; /* Prefetchable memory limit
>> + in case of 64-bit value
>> + This 2 values are mutually exclusive (just
>> as
>> + IO limit), i.e. they can't be >0 both */
>
>
> The same comments as for the SeaBIOS series, can the capability
> be more simple?
> uint32_t bus_res
> uint32_t io_res
> uint32_t mem_res
> uint32_t pref_32_res
> uint64_t pref_64_res
>
In this version I've designed it just as Laszlo suggested -
whenever we have variable-size fields - like IO and prefetchable -
we use mutually exclusive fields.
I think now we should choose one common format and fix it for the future,
otherwise every next version it will cause new questions.
> It is possible I missed some arguments, I'll have another look
> on the thread.
>
> Thanks,
> Marcel
>
>
>
>> +} PCIBridgeQemuCap;
>> +
>> +#define REDHAT_PCI_CAP_QEMU 1
>> +
>> +int pci_bridge_qemu_cap_init(PCIDevice *dev, int cap_offset,
>> + uint8_t bus_reserve, uint32_t io_reserve,
>> + uint16_t mem_reserve, uint64_t
>> pref_reserve,
>> + Error **errp);
>> +
>> #endif /* QEMU_PCI_BRIDGE_H */
>>
>
--
Alexander Bezzubikov
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